| Line 65... |
Line 65... |
C_NR_STAGES_TOTAL : integer := 96;
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C_NR_STAGES_TOTAL : integer := 96;
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C_NR_STAGES_LOW : integer := 32;
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C_NR_STAGES_LOW : integer := 32;
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C_SPLIT_PIPELINE : boolean := true;
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C_SPLIT_PIPELINE : boolean := true;
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C_FIFO_DEPTH : integer := 32;
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C_FIFO_DEPTH : integer := 32;
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C_MEM_STYLE : string := "asym"; -- xil_prim, generic, asym are valid options
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C_MEM_STYLE : string := "asym"; -- xil_prim, generic, asym are valid options
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C_DEVICE : string := "xilinx" -- xilinx, altera are valid options
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C_FPGA_MAN : string := "xilinx" -- xilinx, altera are valid options
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);
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);
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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-- operand memory interface (plb shared memory)
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-- operand memory interface (plb shared memory)
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| Line 120... |
Line 120... |
signal fifo_empty : std_logic;
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signal fifo_empty : std_logic;
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signal fifo_pop : std_logic;
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signal fifo_pop : std_logic;
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signal fifo_nopop : std_logic;
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signal fifo_nopop : std_logic;
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signal fifo_dout : std_logic_vector(31 downto 0);
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signal fifo_dout : std_logic_vector(31 downto 0);
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begin
|
begin
|
|
-- check the parameters
|
|
assert (C_MEM_STYLE="xil_prim" or C_MEM_STYLE="generic" or C_MEM_STYLE="asym")
|
|
report "C_MEM_STYLE incorrect!, it must be one of these: xil_prim, generic or asym" severity failure;
|
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assert (C_FPGA_MAN="xilinx" or C_FPGA_MAN="altera")
|
|
report "C_FPGA_MAN incorrect!, it must be one of these: xilinx or altera" severity failure;
|
|
|
-- The actual multiplier
|
-- The actual multiplier
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the_multiplier : mont_multiplier
|
the_multiplier : mont_multiplier
|
generic map(
|
generic map(
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n => C_NR_BITS_TOTAL,
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n => C_NR_BITS_TOTAL,
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| Line 148... |
Line 153... |
generic map(
|
generic map(
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width => C_NR_BITS_TOTAL,
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width => C_NR_BITS_TOTAL,
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nr_op => nr_op,
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nr_op => nr_op,
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nr_m => nr_m,
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nr_m => nr_m,
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mem_style => C_MEM_STYLE,
|
mem_style => C_MEM_STYLE,
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device => C_DEVICE
|
device => C_FPGA_MAN
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)
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)
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port map(
|
port map(
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data_in => data_in,
|
data_in => data_in,
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data_out => data_out,
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data_out => data_out,
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rw_address => rw_address,
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rw_address => rw_address,
|
