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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [mod_sim_exp_core.vhd] - Diff between revs 75 and 84

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Rev 75 Rev 84
Line 65... Line 65...
    C_NR_STAGES_TOTAL : integer := 96;
    C_NR_STAGES_TOTAL : integer := 96;
    C_NR_STAGES_LOW   : integer := 32;
    C_NR_STAGES_LOW   : integer := 32;
    C_SPLIT_PIPELINE  : boolean := true;
    C_SPLIT_PIPELINE  : boolean := true;
    C_FIFO_DEPTH      : integer := 32;
    C_FIFO_DEPTH      : integer := 32;
    C_MEM_STYLE       : string  := "asym"; -- xil_prim, generic, asym are valid options
    C_MEM_STYLE       : string  := "asym"; -- xil_prim, generic, asym are valid options
    C_DEVICE          : string  := "xilinx"   -- xilinx, altera are valid options
    C_FPGA_MAN        : string  := "xilinx"   -- xilinx, altera are valid options
  );
  );
  port(
  port(
    clk   : in  std_logic;
    clk   : in  std_logic;
    reset : in  std_logic;
    reset : in  std_logic;
      -- operand memory interface (plb shared memory)
      -- operand memory interface (plb shared memory)
Line 120... Line 120...
  signal fifo_empty : std_logic;
  signal fifo_empty : std_logic;
  signal fifo_pop   : std_logic;
  signal fifo_pop   : std_logic;
  signal fifo_nopop : std_logic;
  signal fifo_nopop : std_logic;
  signal fifo_dout  : std_logic_vector(31 downto 0);
  signal fifo_dout  : std_logic_vector(31 downto 0);
begin
begin
 
  -- check the parameters
 
  assert (C_MEM_STYLE="xil_prim" or C_MEM_STYLE="generic" or C_MEM_STYLE="asym")
 
    report "C_MEM_STYLE incorrect!, it must be one of these: xil_prim, generic or asym" severity failure;
 
  assert (C_FPGA_MAN="xilinx" or C_FPGA_MAN="altera")
 
    report "C_FPGA_MAN incorrect!, it must be one of these: xilinx or altera" severity failure;
 
 
  -- The actual multiplier
  -- The actual multiplier
  the_multiplier : mont_multiplier
  the_multiplier : mont_multiplier
  generic map(
  generic map(
    n     => C_NR_BITS_TOTAL,
    n     => C_NR_BITS_TOTAL,
Line 148... Line 153...
  generic map(
  generic map(
    width     => C_NR_BITS_TOTAL,
    width     => C_NR_BITS_TOTAL,
    nr_op     => nr_op,
    nr_op     => nr_op,
    nr_m      => nr_m,
    nr_m      => nr_m,
    mem_style => C_MEM_STYLE,
    mem_style => C_MEM_STYLE,
    device    => C_DEVICE
    device    => C_FPGA_MAN
  )
  )
  port map(
  port map(
    data_in        => data_in,
    data_in        => data_in,
    data_out       => data_out,
    data_out       => data_out,
    rw_address     => rw_address,
    rw_address     => rw_address,

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