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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [mod_sim_exp_pkg.vhd] - Diff between revs 9 and 16

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use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all;
 
 
 
 
package mod_sim_exp_pkg is
package mod_sim_exp_pkg is
 
 
 
  --------------------------------------------------------------------
 
  -- d_flip_flop
 
  --------------------------------------------------------------------
  -- 1-bit D flip-flop with asynchronous active high reset
  -- 1-bit D flip-flop with asynchronous active high reset
 
  -- 
  component d_flip_flop is
  component d_flip_flop is
    port(
    port(
      core_clk : in  std_logic; -- clock signal
      core_clk : in  std_logic; -- clock signal
      reset    : in  std_logic; -- active high reset
      reset    : in  std_logic; -- active high reset
      din      : in  std_logic; -- data in
      din      : in  std_logic; -- data in
      dout     : out std_logic  -- data out
      dout     : out std_logic  -- data out
    );
    );
  end component d_flip_flop;
  end component d_flip_flop;
 
 
 
  --------------------------------------------------------------------
 
  -- register_1b
 
  --------------------------------------------------------------------
  -- 1-bit register with asynchronous reset and clock enable
  -- 1-bit register with asynchronous reset and clock enable
 
  -- 
  component register_1b is
  component register_1b is
    port(
    port(
      core_clk : in  std_logic; -- clock input
      core_clk : in  std_logic; -- clock input
      ce       : in  std_logic; -- clock enable (active high)
      ce       : in  std_logic; -- clock enable (active high)
      reset    : in  std_logic; -- reset (active high)
      reset    : in  std_logic; -- reset (active high)
      din      : in  std_logic; -- data in
      din      : in  std_logic; -- data in
      dout     : out std_logic  -- data out
      dout     : out std_logic  -- data out
    );
    );
  end component register_1b;
  end component register_1b;
 
 
 
  --------------------------------------------------------------------
 
  -- register_n
 
  --------------------------------------------------------------------
  -- n-bit register with asynchronous reset and clock enable
  -- n-bit register with asynchronous reset and clock enable
 
  -- 
  component register_n is
  component register_n is
    generic(
    generic(
      n : integer := 4
      width : integer := 4
    );
    );
    port(
    port(
      core_clk : in  std_logic; -- clock input
      core_clk : in  std_logic; -- clock input
      ce       : in  std_logic; -- clock enable (active high)
      ce       : in  std_logic; -- clock enable (active high)
      reset    : in  std_logic; -- reset (active high)
      reset    : in  std_logic; -- reset (active high)
      din      : in  std_logic_vector((n-1) downto 0);  -- data in (n-bit)
      din      : in  std_logic_vector((width-1) downto 0);  -- data in (width)-bit
      dout     : out std_logic_vector((n-1) downto 0)   -- data out (n-bit)
      dout     : out std_logic_vector((width-1) downto 0)   -- data out (width)-bit
    );
    );
  end component register_n;
  end component register_n;
 
 
  -- 1-bit full adder cell
  --------------------------------------------------------------------
 
  -- cell_1b_adder
 
  --------------------------------------------------------------------
 
  --    1-bit full adder cell using combinatorial logic
 
  --    
  component cell_1b_adder is
  component cell_1b_adder is
    port (
    port (
      -- input operands a, b
      -- input operands a, b
      a    : in  std_logic;
      a    : in  std_logic;
      b    : in  std_logic;
      b    : in  std_logic;
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      -- result out
      -- result out
      r    : out  std_logic
      r    : out  std_logic
    );
    );
  end component cell_1b_adder;
  end component cell_1b_adder;
 
 
  -- 1-bit mux for a standard cell in the montgommery multiplier systolic array
  --------------------------------------------------------------------
 
  -- cell_1b_mux
 
  --------------------------------------------------------------------
 
  --    1-bit mux for a standard cell in the montgommery multiplier 
 
  --    systolic array
 
  -- 
  component cell_1b_mux is
  component cell_1b_mux is
    port (
    port (
      -- input bits
      -- input bits
      my     : in  std_logic;
      my     : in  std_logic;
      y      : in  std_logic;
      y      : in  std_logic;
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      -- mux out
      -- mux out
      result : out std_logic
      result : out std_logic
    );
    );
  end component cell_1b_mux;
  end component cell_1b_mux;
 
 
 
  --------------------------------------------------------------------
 
  -- cell_1b
 
  --------------------------------------------------------------------
  -- 1-bit cell for the systolic array
  -- 1-bit cell for the systolic array
 
  -- 
  component cell_1b is
  component cell_1b is
    port (
    port (
      -- operand input bits (m+y, y and m)
      -- operand input bits (m+y, y and m)
      my   : in  std_logic;
      my   : in  std_logic;
      y    : in  std_logic;
      y    : in  std_logic;
      m    : in  std_logic;
      m    : in  std_logic;
      -- operand x input bit and q (serial)
      -- operand x input bit and q
      x    : in  std_logic;
      x    : in  std_logic;
      q    : in  std_logic;
      q    : in  std_logic;
      -- previous result input bit
      -- previous result input bit
      a    : in  std_logic;
      a    : in  std_logic;
      -- carry's
      -- carry's
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      -- cell result out
      -- cell result out
      r    : out std_logic
      r    : out std_logic
    );
    );
  end component cell_1b;
  end component cell_1b;
 
 
  -- (width)-bit full adder block using cell_1b_adders
  --------------------------------------------------------------------
  -- with buffered carry out
  -- adder_block
 
  --------------------------------------------------------------------
 
  --    (width)-bit full adder block using cell_1b_adders with buffered
 
  --    carry out
 
  -- 
  component adder_block is
  component adder_block is
    generic (
    generic (
      width : integer := 32 --adder operand widths
      width : integer := 32 --adder operand widths
    );
    );
    port (
    port (
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      -- adder result out (width)-bit
      -- adder result out (width)-bit
      r : out std_logic_vector((width-1) downto 0)
      r : out std_logic_vector((width-1) downto 0)
    );
    );
  end component adder_block;
  end component adder_block;
 
 
  -- n-bit adder using adder blocks. works in stages, to prevent large 
  --------------------------------------------------------------------
  -- carry propagation
  -- adder_n
 
  --------------------------------------------------------------------
 
  --    n-bit adder using adder blocks. works in stages, to prevent 
 
  --    large carry propagation. 
 
  --    Result avaiable after (width/block_width) clock cycles
 
  -- 
  component adder_n is
  component adder_n is
    generic (
    generic (
      width       : integer := 1536; -- adder operands width
      width       : integer := 1536; -- adder operands width
      block_width : integer := 8     -- adder blocks size
      block_width : integer := 8     -- adder blocks size
    );
    );

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