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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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package mod_sim_exp_pkg is
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package mod_sim_exp_pkg is
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--------------------------------------------------------------------
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-- d_flip_flop
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--------------------------------------------------------------------
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-- 1-bit D flip-flop with asynchronous active high reset
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-- 1-bit D flip-flop with asynchronous active high reset
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--
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component d_flip_flop is
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component d_flip_flop is
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port(
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port(
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core_clk : in std_logic; -- clock signal
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core_clk : in std_logic; -- clock signal
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reset : in std_logic; -- active high reset
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reset : in std_logic; -- active high reset
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din : in std_logic; -- data in
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din : in std_logic; -- data in
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dout : out std_logic -- data out
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dout : out std_logic -- data out
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);
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);
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end component d_flip_flop;
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end component d_flip_flop;
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--------------------------------------------------------------------
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-- register_1b
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--------------------------------------------------------------------
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-- 1-bit register with asynchronous reset and clock enable
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-- 1-bit register with asynchronous reset and clock enable
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--
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component register_1b is
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component register_1b is
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port(
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port(
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core_clk : in std_logic; -- clock input
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core_clk : in std_logic; -- clock input
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ce : in std_logic; -- clock enable (active high)
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ce : in std_logic; -- clock enable (active high)
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reset : in std_logic; -- reset (active high)
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reset : in std_logic; -- reset (active high)
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din : in std_logic; -- data in
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din : in std_logic; -- data in
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dout : out std_logic -- data out
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dout : out std_logic -- data out
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);
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);
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end component register_1b;
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end component register_1b;
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--------------------------------------------------------------------
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-- register_n
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--------------------------------------------------------------------
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-- n-bit register with asynchronous reset and clock enable
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-- n-bit register with asynchronous reset and clock enable
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--
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component register_n is
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component register_n is
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generic(
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generic(
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n : integer := 4
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width : integer := 4
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);
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);
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port(
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port(
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core_clk : in std_logic; -- clock input
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core_clk : in std_logic; -- clock input
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ce : in std_logic; -- clock enable (active high)
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ce : in std_logic; -- clock enable (active high)
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reset : in std_logic; -- reset (active high)
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reset : in std_logic; -- reset (active high)
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din : in std_logic_vector((n-1) downto 0); -- data in (n-bit)
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din : in std_logic_vector((width-1) downto 0); -- data in (width)-bit
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dout : out std_logic_vector((n-1) downto 0) -- data out (n-bit)
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dout : out std_logic_vector((width-1) downto 0) -- data out (width)-bit
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);
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);
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end component register_n;
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end component register_n;
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-- 1-bit full adder cell
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--------------------------------------------------------------------
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-- cell_1b_adder
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--------------------------------------------------------------------
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-- 1-bit full adder cell using combinatorial logic
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--
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component cell_1b_adder is
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component cell_1b_adder is
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port (
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port (
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-- input operands a, b
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-- input operands a, b
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a : in std_logic;
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a : in std_logic;
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b : in std_logic;
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b : in std_logic;
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Line 113... |
-- result out
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-- result out
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r : out std_logic
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r : out std_logic
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);
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);
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end component cell_1b_adder;
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end component cell_1b_adder;
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-- 1-bit mux for a standard cell in the montgommery multiplier systolic array
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--------------------------------------------------------------------
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-- cell_1b_mux
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--------------------------------------------------------------------
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-- 1-bit mux for a standard cell in the montgommery multiplier
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-- systolic array
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--
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component cell_1b_mux is
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component cell_1b_mux is
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port (
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port (
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-- input bits
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-- input bits
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my : in std_logic;
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my : in std_logic;
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y : in std_logic;
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y : in std_logic;
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Line 133... |
-- mux out
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-- mux out
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result : out std_logic
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result : out std_logic
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);
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);
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end component cell_1b_mux;
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end component cell_1b_mux;
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--------------------------------------------------------------------
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-- cell_1b
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--------------------------------------------------------------------
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-- 1-bit cell for the systolic array
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-- 1-bit cell for the systolic array
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--
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component cell_1b is
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component cell_1b is
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port (
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port (
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-- operand input bits (m+y, y and m)
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-- operand input bits (m+y, y and m)
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my : in std_logic;
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my : in std_logic;
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y : in std_logic;
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y : in std_logic;
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m : in std_logic;
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m : in std_logic;
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-- operand x input bit and q (serial)
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-- operand x input bit and q
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x : in std_logic;
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x : in std_logic;
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q : in std_logic;
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q : in std_logic;
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-- previous result input bit
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-- previous result input bit
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a : in std_logic;
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a : in std_logic;
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-- carry's
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-- carry's
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Line 157... |
-- cell result out
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-- cell result out
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r : out std_logic
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r : out std_logic
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);
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);
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end component cell_1b;
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end component cell_1b;
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-- (width)-bit full adder block using cell_1b_adders
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--------------------------------------------------------------------
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-- with buffered carry out
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-- adder_block
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--------------------------------------------------------------------
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-- (width)-bit full adder block using cell_1b_adders with buffered
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-- carry out
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--
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component adder_block is
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component adder_block is
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generic (
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generic (
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width : integer := 32 --adder operand widths
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width : integer := 32 --adder operand widths
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);
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);
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port (
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port (
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Line 181... |
-- adder result out (width)-bit
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-- adder result out (width)-bit
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r : out std_logic_vector((width-1) downto 0)
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r : out std_logic_vector((width-1) downto 0)
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);
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);
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end component adder_block;
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end component adder_block;
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-- n-bit adder using adder blocks. works in stages, to prevent large
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--------------------------------------------------------------------
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-- carry propagation
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-- adder_n
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--------------------------------------------------------------------
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-- n-bit adder using adder blocks. works in stages, to prevent
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-- large carry propagation.
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-- Result avaiable after (width/block_width) clock cycles
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--
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component adder_n is
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component adder_n is
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generic (
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generic (
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width : integer := 1536; -- adder operands width
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width : integer := 1536; -- adder operands width
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block_width : integer := 8 -- adder blocks size
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block_width : integer := 8 -- adder blocks size
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);
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);
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