OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [mod_sim_exp_pkg.vhd] - Diff between revs 20 and 21

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 20 Rev 21
Line 403... Line 403...
      reset  : in  std_logic; -- reset, clears register
      reset  : in  std_logic; -- reset, clears register
      load_x : in  std_logic; -- load operand into shift register   
      load_x : in  std_logic; -- load operand into shift register   
      next_x : in  std_logic; -- next bit of x
      next_x : in  std_logic; -- next bit of x
      p_sel  : in  std_logic_vector(1 downto 0);  -- pipeline selection
      p_sel  : in  std_logic_vector(1 downto 0);  -- pipeline selection
      -- x operand bit out (serial)
      -- x operand bit out (serial)
      x_i    : out std_logic
      xi     : out std_logic
    );
    );
  end component x_shift_reg;
  end component x_shift_reg;
 
 
  component autorun_cntrl is
  component autorun_cntrl is
    port (
    port (

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.