URL
https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [mod_sim_exp_pkg.vhd] - Diff between revs 25 and 30
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 25 |
Rev 30 |
| Line 691... |
Line 691... |
r_sel : in std_logic; -- result selection: 0 -> pipeline result, 1 -> reducted result
|
r_sel : in std_logic; -- result selection: 0 -> pipeline result, 1 -> reducted result
|
r : out std_logic_vector((width-1) downto 0)
|
r : out std_logic_vector((width-1) downto 0)
|
);
|
);
|
end component sys_stage;
|
end component sys_stage;
|
|
|
|
--------------------------------------------------------------------
|
|
-- sys_last_cell_logic
|
|
--------------------------------------------------------------------
|
|
-- logic needed as the last piece in the systolic array pipeline
|
|
-- calculates the last 2 bits of the cell_result and finishes the reduction
|
|
-- also generates the result selection signal
|
|
--
|
|
component sys_last_cell_logic is
|
|
port (
|
|
core_clk : in std_logic; -- clock input
|
|
reset : in std_logic;
|
|
a_0 : out std_logic; -- a_msb for last stage
|
|
cin : in std_logic; -- cout from last stage
|
|
red_cin : in std_logic; -- red_cout from last stage
|
|
r_sel : out std_logic; -- result selection bit
|
|
start : in std_logic -- done signal from last stage
|
|
);
|
|
end component sys_last_cell_logic;
|
|
|
--------------------------------------------------------------------
|
--------------------------------------------------------------------
|
-- sys_pipeline
|
-- sys_pipeline
|
--------------------------------------------------------------------
|
--------------------------------------------------------------------
|
-- the pipelined systolic array for a montgommery multiplier
|
-- the pipelined systolic array for a montgommery multiplier
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.