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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [mod_sim_exp_pkg.vhd] - Diff between revs 30 and 31
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Rev 31 |
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Line 711... |
start : in std_logic -- done signal from last stage
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start : in std_logic -- done signal from last stage
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);
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);
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end component sys_last_cell_logic;
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end component sys_last_cell_logic;
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--------------------------------------------------------------------
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--------------------------------------------------------------------
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-- sys_first_cell_logic
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--------------------------------------------------------------------
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-- logic needed as the first piece in the systolic array pipeline
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-- calculates the first my_cout and generates q signal
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--
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component sys_first_cell_logic is
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port (
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m0 : in std_logic; -- lsb from m operand
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y0 : in std_logic; -- lsb from y operand
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my_cout : out std_logic; -- my_cin for first stage
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xi : in std_logic; -- xi operand input
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xout : out std_logic; -- xin for first stage
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qout : out std_logic; -- qin for first stage
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cout : out std_logic; -- cin for first stage
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a_0 : in std_logic; -- a_0 from first stage
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red_cout : out std_logic -- red_cin for first stage
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);
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end component sys_first_cell_logic;
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--------------------------------------------------------------------
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-- sys_pipeline
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-- sys_pipeline
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--------------------------------------------------------------------
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--------------------------------------------------------------------
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-- the pipelined systolic array for a montgommery multiplier
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-- the pipelined systolic array for a montgommery multiplier
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-- contains a structural description of the pipeline using the systolic stages
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-- contains a structural description of the pipeline using the systolic stages
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--
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--
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