URL
https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [mod_sim_exp_pkg.vhd] - Diff between revs 31 and 34
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 31 |
Rev 34 |
| Line 609... |
Line 609... |
-- don't care in case of modulus
|
-- don't care in case of modulus
|
-- bits: 5-0 -> modulus_addr / operand_addr resp.
|
-- bits: 5-0 -> modulus_addr / operand_addr resp.
|
|
|
-- operand interface (multiplier side)
|
-- operand interface (multiplier side)
|
op_sel : in std_logic_vector(1 downto 0);
|
op_sel : in std_logic_vector(1 downto 0);
|
xy_out : out std_logic_vector(1535 downto 0);
|
xy_out : out std_logic_vector((n-1) downto 0);
|
m : out std_logic_vector(1535 downto 0);
|
m : out std_logic_vector((n-1) downto 0);
|
result_in : in std_logic_vector(1535 downto 0);
|
result_in : in std_logic_vector((n-1) downto 0);
|
-- control signals
|
-- control signals
|
load_op : in std_logic;
|
load_op : in std_logic;
|
load_m : in std_logic;
|
load_m : in std_logic;
|
load_result : in std_logic;
|
load_result : in std_logic;
|
result_dest_op : in std_logic_vector(1 downto 0);
|
result_dest_op : in std_logic_vector(1 downto 0);
|
© copyright 1999-2025
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.