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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [mod_sim_exp_pkg.vhd] - Diff between revs 34 and 37

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use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all;
 
 
 
 
package mod_sim_exp_pkg is
package mod_sim_exp_pkg is
 
  --------------------------------------------------------------------
 
  ------------------------- CORE PARAMETERS --------------------------
 
  --------------------------------------------------------------------
 
  -- These 4 parameters affect core workings
 
  constant nr_bits_total    : integer := 1536;
 
  constant nr_stages_total  : integer := 96;
 
  constant nr_stages_low    : integer := 32;
 
  constant split_pipeline   : boolean := true;
 
 
 
  -- extra calculated parameters
 
  constant nr_bits_low      : integer := (nr_bits_total/nr_stages_total)*nr_stages_low;
 
  constant nr_bits_high     : integer := nr_bits_total-nr_bits_low;
 
  constant nr_stages_high   : integer := nr_stages_total-nr_stages_low;
 
 
 
 
 
  --------------------------------------------------------------------
 
  ---------------------- COMPONENT DECLARATIONS ----------------------
 
  --------------------------------------------------------------------
 
 
  --------------------------------------------------------------------
  --------------------------------------------------------------------
  -- d_flip_flop
  -- d_flip_flop
  --------------------------------------------------------------------
  --------------------------------------------------------------------
  --    1-bit D flip-flop with asynchronous active high reset
  --    1-bit D flip-flop with asynchronous active high reset
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  --    * result is avaiable on the r bus
  --    * result is avaiable on the r bus
  -- 
  -- 
  component mont_mult_sys_pipeline is
  component mont_mult_sys_pipeline is
    generic (
    generic (
      n          : integer := 1536; -- width of the operands
      n          : integer := 1536; -- width of the operands
      nr_stages  : integer := 96; -- total number of stages
      t  : integer := 96;   -- total number of stages
      stages_low : integer := 32  -- lower number of stages
      tl : integer := 32    -- lower number of stages
    );
    );
    port (
    port (
      -- clock input
      -- clock input
      core_clk : in std_logic;
      core_clk : in std_logic;
      -- operand inputs
      -- operand inputs
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  --    contains a structural description of the pipeline using the systolic stages
  --    contains a structural description of the pipeline using the systolic stages
  -- 
  -- 
  component sys_pipeline is
  component sys_pipeline is
    generic(
    generic(
      n  : integer := 1536; -- width of the operands (# bits)
      n  : integer := 1536; -- width of the operands (# bits)
      t  : integer := 192;  -- total number of stages (divider of n) >= 2
      t  : integer := 192;  -- total number of stages (minimum 2)
      tl : integer := 64    -- lower number of stages (best take t = sqrt(n))
      tl : integer := 64;   -- lower number of stages (minimum 1)
 
      split : boolean := true -- if true the pipeline wil be split in 2 parts,
 
                              -- if false there are no lower stages, only t counts
    );
    );
    port(
    port(
      -- clock input
      -- clock input
      core_clk : in  std_logic;
      core_clk : in  std_logic;
      -- modulus and y opperand input (n)-bit
      -- modulus and y opperand input (n)-bit
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  end component sys_pipeline;
  end component sys_pipeline;
 
 
  component mont_multiplier is
  component mont_multiplier is
  generic (
  generic (
    n          : integer := 1536; -- width of the operands
    n          : integer := 1536; -- width of the operands
    nr_stages  : integer := 96; -- total number of stages
    t     : integer := 96;    -- total number of stages (minimum 2)
    stages_low : integer := 32  -- lower number of stages
    tl    : integer := 32;    -- lower number of stages (minimum 1)
 
    split : boolean := true   -- if true the pipeline wil be split in 2 parts,
 
                              -- if false there are no lower stages, only t counts
  );
  );
  port (
  port (
    -- clock input
    -- clock input
    core_clk : in std_logic;
    core_clk : in std_logic;
    -- operand inputs
    -- operand inputs

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