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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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package mod_sim_exp_pkg is
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package mod_sim_exp_pkg is
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--------------------------------------------------------------------
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------------------------- CORE PARAMETERS --------------------------
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--------------------------------------------------------------------
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-- These 4 parameters affect core workings
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constant nr_bits_total : integer := 1536;
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constant nr_stages_total : integer := 96;
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constant nr_stages_low : integer := 32;
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constant split_pipeline : boolean := true;
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-- extra calculated parameters
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constant nr_bits_low : integer := (nr_bits_total/nr_stages_total)*nr_stages_low;
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constant nr_bits_high : integer := nr_bits_total-nr_bits_low;
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constant nr_stages_high : integer := nr_stages_total-nr_stages_low;
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--------------------------------------------------------------------
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---------------------- COMPONENT DECLARATIONS ----------------------
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--------------------------------------------------------------------
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--------------------------------------------------------------------
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--------------------------------------------------------------------
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-- d_flip_flop
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-- d_flip_flop
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--------------------------------------------------------------------
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--------------------------------------------------------------------
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-- 1-bit D flip-flop with asynchronous active high reset
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-- 1-bit D flip-flop with asynchronous active high reset
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-- * result is avaiable on the r bus
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-- * result is avaiable on the r bus
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--
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--
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component mont_mult_sys_pipeline is
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component mont_mult_sys_pipeline is
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generic (
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generic (
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n : integer := 1536; -- width of the operands
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n : integer := 1536; -- width of the operands
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nr_stages : integer := 96; -- total number of stages
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t : integer := 96; -- total number of stages
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stages_low : integer := 32 -- lower number of stages
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tl : integer := 32 -- lower number of stages
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);
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);
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port (
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port (
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-- clock input
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-- clock input
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core_clk : in std_logic;
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core_clk : in std_logic;
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-- operand inputs
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-- operand inputs
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-- contains a structural description of the pipeline using the systolic stages
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-- contains a structural description of the pipeline using the systolic stages
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--
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--
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component sys_pipeline is
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component sys_pipeline is
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generic(
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generic(
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n : integer := 1536; -- width of the operands (# bits)
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n : integer := 1536; -- width of the operands (# bits)
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t : integer := 192; -- total number of stages (divider of n) >= 2
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t : integer := 192; -- total number of stages (minimum 2)
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tl : integer := 64 -- lower number of stages (best take t = sqrt(n))
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tl : integer := 64; -- lower number of stages (minimum 1)
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split : boolean := true -- if true the pipeline wil be split in 2 parts,
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-- if false there are no lower stages, only t counts
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);
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);
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port(
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port(
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-- clock input
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-- clock input
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core_clk : in std_logic;
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core_clk : in std_logic;
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-- modulus and y opperand input (n)-bit
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-- modulus and y opperand input (n)-bit
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end component sys_pipeline;
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end component sys_pipeline;
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component mont_multiplier is
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component mont_multiplier is
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generic (
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generic (
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n : integer := 1536; -- width of the operands
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n : integer := 1536; -- width of the operands
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nr_stages : integer := 96; -- total number of stages
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t : integer := 96; -- total number of stages (minimum 2)
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stages_low : integer := 32 -- lower number of stages
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tl : integer := 32; -- lower number of stages (minimum 1)
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split : boolean := true -- if true the pipeline wil be split in 2 parts,
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-- if false there are no lower stages, only t counts
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);
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);
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port (
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port (
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-- clock input
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-- clock input
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core_clk : in std_logic;
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core_clk : in std_logic;
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-- operand inputs
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-- operand inputs
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