| Line 571... |
Line 571... |
modulus_in : in std_logic_vector(31 downto 0);
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modulus_in : in std_logic_vector(31 downto 0);
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modulus_out : out std_logic_vector(1535 downto 0)
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modulus_out : out std_logic_vector(1535 downto 0)
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);
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);
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end component modulus_ram;
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end component modulus_ram;
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|
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--------------------------------------------------------------------
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-- mont_ctrl
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|
--------------------------------------------------------------------
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|
-- This module controls the montgommery mutliplier and controls traffic between
|
|
-- RAM and multiplier. Also contains the autorun logic for exponentiations.
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|
--
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component mont_ctrl is
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component mont_ctrl is
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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-- bus side
|
-- bus side
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| Line 583... |
Line 589... |
y_sel_single : in std_logic_vector(1 downto 0);
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y_sel_single : in std_logic_vector(1 downto 0);
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run_auto : in std_logic;
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run_auto : in std_logic;
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op_buffer_empty : in std_logic;
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op_buffer_empty : in std_logic;
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op_sel_buffer : in std_logic_vector(31 downto 0);
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op_sel_buffer : in std_logic_vector(31 downto 0);
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read_buffer : out std_logic;
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read_buffer : out std_logic;
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buffer_noread : in std_logic;
|
|
done : out std_logic;
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done : out std_logic;
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calc_time : out std_logic;
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calc_time : out std_logic;
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-- multiplier side
|
-- multiplier side
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op_sel : out std_logic_vector(1 downto 0);
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op_sel : out std_logic_vector(1 downto 0);
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load_x : out std_logic;
|
load_x : out std_logic;
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| Line 611... |
Line 616... |
doutb : out std_logic_vector(31 downto 0)
|
doutb : out std_logic_vector(31 downto 0)
|
);
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);
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end component operand_dp;
|
end component operand_dp;
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|
|
component operand_mem is
|
component operand_mem is
|
generic(n : integer := 1536
|
generic(
|
|
n : integer := 1536
|
);
|
);
|
port(
|
port(
|
-- data interface (plb side)
|
-- data interface (plb side)
|
data_in : in std_logic_vector(31 downto 0);
|
data_in : in std_logic_vector(31 downto 0);
|
data_out : out std_logic_vector(31 downto 0);
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data_out : out std_logic_vector(31 downto 0);
|
rw_address : in std_logic_vector(8 downto 0);
|
rw_address : in std_logic_vector(8 downto 0);
|
|
write_enable : in std_logic;
|
-- address structure:
|
-- address structure:
|
-- bit: 8 -> '1': modulus
|
-- bit: 8 -> '1': modulus
|
-- '0': operands
|
-- '0': operands
|
-- bits: 7-6 -> operand_in_sel in case of bit 8 = '0'
|
-- bits: 7-6 -> operand_in_sel in case of bit 8 = '0'
|
-- don't care in case of modulus
|
-- don't care in case of modulus
|
| Line 631... |
Line 638... |
op_sel : in std_logic_vector(1 downto 0);
|
op_sel : in std_logic_vector(1 downto 0);
|
xy_out : out std_logic_vector((n-1) downto 0);
|
xy_out : out std_logic_vector((n-1) downto 0);
|
m : out std_logic_vector((n-1) downto 0);
|
m : out std_logic_vector((n-1) downto 0);
|
result_in : in std_logic_vector((n-1) downto 0);
|
result_in : in std_logic_vector((n-1) downto 0);
|
-- control signals
|
-- control signals
|
load_op : in std_logic;
|
|
load_m : in std_logic;
|
|
load_result : in std_logic;
|
load_result : in std_logic;
|
result_dest_op : in std_logic_vector(1 downto 0);
|
result_dest_op : in std_logic_vector(1 downto 0);
|
collision : out std_logic;
|
collision : out std_logic;
|
-- system clock
|
-- system clock
|
clk : in std_logic
|
clk : in std_logic
|
