| Line 774... |
Line 774... |
component mod_sim_exp_core is
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component mod_sim_exp_core is
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generic(
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generic(
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C_NR_BITS_TOTAL : integer := 1536;
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C_NR_BITS_TOTAL : integer := 1536;
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C_NR_STAGES_TOTAL : integer := 96;
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C_NR_STAGES_TOTAL : integer := 96;
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C_NR_STAGES_LOW : integer := 32;
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C_NR_STAGES_LOW : integer := 32;
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C_SPLIT_PIPELINE : boolean := true
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C_SPLIT_PIPELINE : boolean := true;
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C_NR_OP : integer := 4;
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C_NR_M : integer := 2;
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C_FIFO_DEPTH : integer := 32
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);
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);
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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-- operand memory interface (plb shared memory)
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-- operand memory interface (plb shared memory)
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| Line 798... |
Line 801... |
ready : out std_logic; -- calculations done
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ready : out std_logic; -- calculations done
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x_sel_single : in std_logic_vector (1 downto 0); -- single multiplication x operand selection
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x_sel_single : in std_logic_vector (1 downto 0); -- single multiplication x operand selection
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y_sel_single : in std_logic_vector (1 downto 0); -- single multiplication y operand selection
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y_sel_single : in std_logic_vector (1 downto 0); -- single multiplication y operand selection
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dest_op_single : in std_logic_vector (1 downto 0); -- result destination operand selection
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dest_op_single : in std_logic_vector (1 downto 0); -- result destination operand selection
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p_sel : in std_logic_vector (1 downto 0); -- pipeline part selection
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p_sel : in std_logic_vector (1 downto 0); -- pipeline part selection
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calc_time : out std_logic
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calc_time : out std_logic;
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modulus_sel : in std_logic_vector(log2(C_NR_M)-1 downto 0)
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);
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);
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end component mod_sim_exp_core;
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end component mod_sim_exp_core;
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end package mod_sim_exp_pkg;
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end package mod_sim_exp_pkg;
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