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URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [mod_sim_exp_pkg.vhd] - Diff between revs 63 and 65

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Rev 63 Rev 65
Line 774... Line 774...
  component mod_sim_exp_core is
  component mod_sim_exp_core is
    generic(
    generic(
      C_NR_BITS_TOTAL : integer := 1536;
      C_NR_BITS_TOTAL : integer := 1536;
      C_NR_STAGES_TOTAL : integer := 96;
      C_NR_STAGES_TOTAL : integer := 96;
      C_NR_STAGES_LOW : integer := 32;
      C_NR_STAGES_LOW : integer := 32;
      C_SPLIT_PIPELINE : boolean := true
      C_SPLIT_PIPELINE  : boolean := true;
 
      C_NR_OP           : integer := 4;
 
      C_NR_M            : integer := 2;
 
      C_FIFO_DEPTH      : integer := 32
    );
    );
    port(
    port(
      clk   : in  std_logic;
      clk   : in  std_logic;
      reset : in  std_logic;
      reset : in  std_logic;
        -- operand memory interface (plb shared memory)
        -- operand memory interface (plb shared memory)
Line 798... Line 801...
      ready          : out std_logic; -- calculations done
      ready          : out std_logic; -- calculations done
      x_sel_single   : in  std_logic_vector (1 downto 0); -- single multiplication x operand selection
      x_sel_single   : in  std_logic_vector (1 downto 0); -- single multiplication x operand selection
      y_sel_single   : in  std_logic_vector (1 downto 0); -- single multiplication y operand selection
      y_sel_single   : in  std_logic_vector (1 downto 0); -- single multiplication y operand selection
      dest_op_single : in  std_logic_vector (1 downto 0); -- result destination operand selection
      dest_op_single : in  std_logic_vector (1 downto 0); -- result destination operand selection
      p_sel          : in  std_logic_vector (1 downto 0); -- pipeline part selection
      p_sel          : in  std_logic_vector (1 downto 0); -- pipeline part selection
      calc_time      : out std_logic
      calc_time      : out std_logic;
 
      modulus_sel    : in std_logic_vector(log2(C_NR_M)-1 downto 0)
    );
    );
  end component mod_sim_exp_core;
  end component mod_sim_exp_core;
 
 
 
 
end package mod_sim_exp_pkg;
end package mod_sim_exp_pkg;
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