| Line 465... |
Line 465... |
end component mont_multiplier;
|
end component mont_multiplier;
|
|
|
|
|
------------------------------ MEMORY ------------------------------
|
------------------------------ MEMORY ------------------------------
|
|
|
|
-------------------------- xil_prim specific -----------------------
|
--------------------------------------------------------------------
|
--------------------------------------------------------------------
|
-- operand_dp
|
-- operand_dp
|
--------------------------------------------------------------------
|
--------------------------------------------------------------------
|
-- true dual port RAM 512x4, uses xilinx primitives
|
-- true dual port RAM 512x4, uses xilinx primitives
|
--
|
--
|
| Line 501... |
Line 502... |
douta : out std_logic_vector(511 downto 0)
|
douta : out std_logic_vector(511 downto 0)
|
);
|
);
|
end component operands_sp;
|
end component operands_sp;
|
|
|
--------------------------------------------------------------------
|
--------------------------------------------------------------------
|
|
-- fifo_primitive
|
|
--------------------------------------------------------------------
|
|
-- a xilinx fifo primitive wrapper
|
|
--
|
|
component fifo_primitive is
|
|
port (
|
|
clk : in std_logic;
|
|
din : in std_logic_vector (31 downto 0);
|
|
dout : out std_logic_vector (31 downto 0);
|
|
empty : out std_logic;
|
|
full : out std_logic;
|
|
push : in std_logic;
|
|
pop : in std_logic;
|
|
reset : in std_logic;
|
|
nopop : out std_logic;
|
|
nopush : out std_logic
|
|
);
|
|
end component fifo_primitive;
|
|
|
|
--------------------------------------------------------------------
|
|
-- operand_ram
|
|
--------------------------------------------------------------------
|
|
-- RAM for the operands, fixed width of 1536-bit and depth of 4
|
|
-- uses xilinx primitives
|
|
--
|
|
component operand_ram is
|
|
port(
|
|
-- global ports
|
|
clk : in std_logic;
|
|
collision : out std_logic;
|
|
-- bus side connections (32-bit serial)
|
|
operand_addr : in std_logic_vector(5 downto 0);
|
|
operand_in : in std_logic_vector(31 downto 0);
|
|
operand_in_sel : in std_logic_vector(1 downto 0);
|
|
result_out : out std_logic_vector(31 downto 0);
|
|
write_operand : in std_logic;
|
|
-- multiplier side connections (1536 bit parallel)
|
|
result_dest_op : in std_logic_vector(1 downto 0);
|
|
operand_out : out std_logic_vector(1535 downto 0);
|
|
operand_out_sel : in std_logic_vector(1 downto 0); -- controlled by bus side
|
|
write_result : in std_logic;
|
|
result_in : in std_logic_vector(1535 downto 0)
|
|
);
|
|
end component operand_ram;
|
|
|
|
--------------------------------------------------------------------
|
|
-- modulus_ram
|
|
--------------------------------------------------------------------
|
|
-- RAM for the modulus, fixed width of 1536-bit, uses xilinx primitives
|
|
--
|
|
component modulus_ram is
|
|
port(
|
|
clk : in std_logic;
|
|
modulus_addr : in std_logic_vector(5 downto 0);
|
|
write_modulus : in std_logic;
|
|
modulus_in : in std_logic_vector(31 downto 0);
|
|
modulus_out : out std_logic_vector(1535 downto 0)
|
|
);
|
|
end component modulus_ram;
|
|
|
|
|
|
------------------------- generic modules --------------------------
|
|
|
|
--------------------------------------------------------------------
|
-- dpram_generic
|
-- dpram_generic
|
--------------------------------------------------------------------
|
--------------------------------------------------------------------
|
-- behavorial description of a dual port ram with one 32-bit
|
-- behavorial description of a dual port ram with one 32-bit
|
-- write port and one 32-bit read port
|
-- write port and one 32-bit read port
|
--
|
--
|
| Line 549... |
Line 614... |
doutB : out std_logic_vector(31 downto 0)
|
doutB : out std_logic_vector(31 downto 0)
|
);
|
);
|
end component tdpram_generic;
|
end component tdpram_generic;
|
|
|
--------------------------------------------------------------------
|
--------------------------------------------------------------------
|
-- fifo_primitive
|
|
--------------------------------------------------------------------
|
|
-- a xilinx fifo primitive wrapper
|
|
--
|
|
component fifo_primitive is
|
|
port (
|
|
clk : in std_logic;
|
|
din : in std_logic_vector (31 downto 0);
|
|
dout : out std_logic_vector (31 downto 0);
|
|
empty : out std_logic;
|
|
full : out std_logic;
|
|
push : in std_logic;
|
|
pop : in std_logic;
|
|
reset : in std_logic;
|
|
nopop : out std_logic;
|
|
nopush : out std_logic
|
|
);
|
|
end component fifo_primitive;
|
|
|
|
--------------------------------------------------------------------
|
|
-- fifo_generic
|
-- fifo_generic
|
--------------------------------------------------------------------
|
--------------------------------------------------------------------
|
-- a behavorial implementation of a fifo that is designed to
|
-- a behavorial implementation of a fifo that is designed to
|
-- infer blockram
|
-- infer blockram
|
--
|
--
|
| Line 593... |
Line 638... |
nopush : out std_logic
|
nopush : out std_logic
|
);
|
);
|
end component fifo_generic;
|
end component fifo_generic;
|
|
|
--------------------------------------------------------------------
|
--------------------------------------------------------------------
|
-- modulus_ram
|
|
--------------------------------------------------------------------
|
|
-- RAM for the modulus, fixed width of 1536-bit, uses xilinx primitives
|
|
--
|
|
component modulus_ram is
|
|
port(
|
|
clk : in std_logic;
|
|
modulus_addr : in std_logic_vector(5 downto 0);
|
|
write_modulus : in std_logic;
|
|
modulus_in : in std_logic_vector(31 downto 0);
|
|
modulus_out : out std_logic_vector(1535 downto 0)
|
|
);
|
|
end component modulus_ram;
|
|
|
|
--------------------------------------------------------------------
|
|
-- modulus_ram_gen
|
-- modulus_ram_gen
|
--------------------------------------------------------------------
|
--------------------------------------------------------------------
|
-- behavorial description of a RAM to hold the modulus, with
|
-- structural description of a RAM to hold the modulus, with
|
-- adjustable width and depth(nr of moduluses)
|
-- adjustable width and depth(nr of moduluses)
|
--
|
--
|
component modulus_ram_gen is
|
component modulus_ram_gen is
|
generic(
|
generic(
|
width : integer := 1536; -- must be a multiple of 32
|
width : integer := 1536; -- must be a multiple of 32
|
| Line 661... |
Line 691... |
write_result : in std_logic; -- write enable for multiplier side
|
write_result : in std_logic; -- write enable for multiplier side
|
result_in : in std_logic_vector(width-1 downto 0) -- result to write from multiplier
|
result_in : in std_logic_vector(width-1 downto 0) -- result to write from multiplier
|
);
|
);
|
end component operand_ram_gen;
|
end component operand_ram_gen;
|
|
|
|
|
|
|
|
------------------------ asymmetric modules ------------------------
|
|
|
--------------------------------------------------------------------
|
--------------------------------------------------------------------
|
-- operand_ram
|
-- dpram_asym
|
--------------------------------------------------------------------
|
--------------------------------------------------------------------
|
-- RAM for the operands, fixed width of 1536-bit and depth of 4
|
-- behavorial description of an asymmetric dual port ram
|
-- uses xilinx primitives
|
-- with one (wrwidth)-bit write port and one 32-bit read
|
|
-- port. Made using the templates of xilinx and altera for
|
|
-- asymmetric ram.
|
--
|
--
|
component operand_ram is
|
component dpram_asym is
|
port( -- write_operand_ack voorzien?
|
generic(
|
-- global ports
|
rddepth : integer := 4; -- nr of 32-bit words
|
|
wrwidth : integer := 2; -- write width, must be smaller than or equal to 32
|
|
device : string := "xilinx" -- device template to use
|
|
);
|
|
port(
|
clk : in std_logic;
|
clk : in std_logic;
|
collision : out std_logic;
|
-- write port
|
-- bus side connections (32-bit serial)
|
waddr : in std_logic_vector(log2((rddepth*32)/wrwidth)-1 downto 0);
|
operand_addr : in std_logic_vector(5 downto 0);
|
we : in std_logic;
|
operand_in : in std_logic_vector(31 downto 0);
|
din : in std_logic_vector(wrwidth-1 downto 0);
|
operand_in_sel : in std_logic_vector(1 downto 0);
|
-- read port
|
result_out : out std_logic_vector(31 downto 0);
|
raddr : in std_logic_vector(log2(rddepth)-1 downto 0);
|
write_operand : in std_logic;
|
dout : out std_logic_vector(31 downto 0)
|
-- multiplier side connections (1536 bit parallel)
|
|
result_dest_op : in std_logic_vector(1 downto 0);
|
|
operand_out : out std_logic_vector(1535 downto 0);
|
|
operand_out_sel : in std_logic_vector(1 downto 0); -- controlled by bus side
|
|
write_result : in std_logic;
|
|
result_in : in std_logic_vector(1535 downto 0)
|
|
);
|
);
|
end component operand_ram;
|
end component dpram_asym;
|
|
|
|
--------------------------------------------------------------------
|
|
-- dpramblock_asym
|
|
--------------------------------------------------------------------
|
|
-- structural description of an asymmetric dual port ram
|
|
-- with one 32-bit write port and one (width)-bit read
|
|
-- port.
|
|
--
|
|
component dpramblock_asym is
|
|
generic(
|
|
width : integer := 256; -- read width
|
|
depth : integer := 2; -- nr of (width)-bit words
|
|
device : string := "xilinx"
|
|
);
|
|
port(
|
|
clk : in std_logic;
|
|
-- write port
|
|
waddr : in std_logic_vector(log2((width*depth)/32)-1 downto 0);
|
|
we : in std_logic;
|
|
din : in std_logic_vector(31 downto 0);
|
|
-- read port
|
|
raddr : in std_logic_vector(log2(depth)-1 downto 0);
|
|
dout : out std_logic_vector(width-1 downto 0)
|
|
);
|
|
end component dpramblock_asym;
|
|
|
component operand_mem is
|
--------------------------------------------------------------------
|
|
-- tdpram_asym
|
|
--------------------------------------------------------------------
|
|
-- behavorial description of an asymmetric true dual port
|
|
-- ram with one (widthA)-bit read/write port and one 32-bit
|
|
-- read/write port. Made using the templates of xilinx and
|
|
-- altera for asymmetric ram.
|
|
--
|
|
component tdpram_asym is
|
generic(
|
generic(
|
n : integer := 1536
|
depthB : integer := 4; -- nr of 32-bit words
|
|
widthA : integer := 2; -- port A width, must be smaller than or equal to 32
|
|
device : string := "xilinx"
|
);
|
);
|
port(
|
port(
|
-- data interface (plb side)
|
clk : in std_logic;
|
data_in : in std_logic_vector(31 downto 0);
|
-- port A (widthA)-bit
|
data_out : out std_logic_vector(31 downto 0);
|
addrA : in std_logic_vector(log2((depthB*32)/widthA)-1 downto 0);
|
rw_address : in std_logic_vector(8 downto 0);
|
weA : in std_logic;
|
write_enable : in std_logic;
|
dinA : in std_logic_vector(widthA-1 downto 0);
|
-- address structure:
|
doutA : out std_logic_vector(widthA-1 downto 0);
|
-- bit: 8 -> '1': modulus
|
-- port B 32-bit
|
-- '0': operands
|
addrB : in std_logic_vector(log2(depthB)-1 downto 0);
|
-- bits: 7-6 -> operand_in_sel in case of bit 8 = '0'
|
weB : in std_logic;
|
-- don't care in case of modulus
|
dinB : in std_logic_vector(31 downto 0);
|
-- bits: 5-0 -> modulus_addr / operand_addr resp.
|
doutB : out std_logic_vector(31 downto 0)
|
|
);
|
|
end component tdpram_asym;
|
|
|
-- operand interface (multiplier side)
|
--------------------------------------------------------------------
|
op_sel : in std_logic_vector(1 downto 0);
|
-- tdpramblock_asym
|
xy_out : out std_logic_vector((n-1) downto 0);
|
--------------------------------------------------------------------
|
m : out std_logic_vector((n-1) downto 0);
|
-- structural description of an asymmetric true dual port
|
result_in : in std_logic_vector((n-1) downto 0);
|
-- ram with one 32-bit read/write port and one (width)-bit
|
-- control signals
|
-- read/write port.
|
load_result : in std_logic;
|
--
|
result_dest_op : in std_logic_vector(1 downto 0);
|
component tdpramblock_asym is
|
collision : out std_logic;
|
generic (
|
-- system clock
|
depth : integer := 4; -- nr of (width)-bit words
|
clk : in std_logic
|
width : integer := 512; -- width of portB
|
|
device : string := "xilinx"
|
);
|
);
|
end component operand_mem;
|
port (
|
|
clk : in std_logic;
|
|
-- port A 32-bit
|
|
addrA : in std_logic_vector(log2((width*depth)/32)-1 downto 0);
|
|
weA : in std_logic;
|
|
dinA : in std_logic_vector(31 downto 0);
|
|
doutA : out std_logic_vector(31 downto 0);
|
|
-- port B (width)-bit
|
|
addrB : in std_logic_vector(log2(depth)-1 downto 0);
|
|
weB : in std_logic;
|
|
dinB : in std_logic_vector(width-1 downto 0);
|
|
doutB : out std_logic_vector(width-1 downto 0)
|
|
);
|
|
end component tdpramblock_asym;
|
|
|
|
--------------------------------------------------------------------
|
|
-- modulus_ram_asym
|
|
--------------------------------------------------------------------
|
|
-- BRAM memory and logic to store the modulus, due to the
|
|
-- achitecture, a minimum depth of 2 is needed for this
|
|
-- module to be inferred into blockram, this version is
|
|
-- slightly more performant than modulus_ram_gen and uses
|
|
-- less resources. but does not work on every fpga, only
|
|
-- the ones that support asymmetric rams.
|
|
--
|
|
component modulus_ram_asym is
|
|
generic(
|
|
width : integer := 1536; -- must be a multiple of 32
|
|
depth : integer := 2; -- nr of moduluses
|
|
device : string := "xilinx"
|
|
);
|
|
port(
|
|
clk : in std_logic;
|
|
-- bus side
|
|
write_modulus : in std_logic; -- write enable
|
|
modulus_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- modulus operand to write to
|
|
modulus_addr : in std_logic_vector(log2((width)/32)-1 downto 0); -- modulus word(32-bit) address
|
|
modulus_in : in std_logic_vector(31 downto 0); -- modulus word data in
|
|
modulus_sel : in std_logic_vector(log2(depth)-1 downto 0); -- selects the modulus to use for multiplications
|
|
-- multiplier side
|
|
modulus_out : out std_logic_vector(width-1 downto 0)
|
|
);
|
|
end component modulus_ram_asym;
|
|
|
--------------------------------------------------------------------
|
--------------------------------------------------------------------
|
-- operand_mem_gen
|
-- operand_ram_asym
|
--------------------------------------------------------------------
|
--------------------------------------------------------------------
|
-- generic description of the cores memory, places the modulus
|
-- BRAM memory and logic to store the operands, due to the
|
-- and operands in one addres and data bus
|
-- achitecture, a minimum depth of 2 is needed for this
|
|
-- module to be inferred into blockram, this version is
|
|
-- slightly more performant than operand_ram_gen and uses
|
|
-- less resources. but does not work on every fpga, only
|
|
-- the ones that support asymmetric rams.
|
|
--
|
|
component operand_ram_asym is
|
|
generic(
|
|
width : integer := 1536; -- width of the operands
|
|
depth : integer := 4; -- nr of operands
|
|
device : string := "xilinx"
|
|
);
|
|
port(
|
|
-- global ports
|
|
clk : in std_logic;
|
|
collision : out std_logic; -- 1 if simultaneous write on RAM
|
|
-- bus side connections (32-bit serial)
|
|
write_operand : in std_logic; -- write_enable
|
|
operand_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to write to
|
|
operand_addr : in std_logic_vector(log2(width/32)-1 downto 0); -- address of operand word to write
|
|
operand_in : in std_logic_vector(31 downto 0); -- operand word(32-bit) to write
|
|
result_out : out std_logic_vector(31 downto 0); -- operand out, reading is always result operand
|
|
operand_out_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to give to multiplier
|
|
-- multiplier side connections (width-bit parallel)
|
|
result_dest_op : in std_logic_vector(log2(depth)-1 downto 0); -- operand select for result
|
|
operand_out : out std_logic_vector(width-1 downto 0); -- operand out to multiplier
|
|
write_result : in std_logic; -- write enable for multiplier side
|
|
result_in : in std_logic_vector(width-1 downto 0) -- result to write from multiplier
|
|
);
|
|
end component operand_ram_asym;
|
|
|
|
--------------------------------------------------------------------
|
|
-- operand_mem
|
|
--------------------------------------------------------------------
|
|
-- RAM memory and logic to the store operands and the
|
|
-- modulus for the montgomery multiplier, the user has a
|
|
-- choise between 3 memory styles, more detail in the
|
|
-- documentation.
|
--
|
--
|
-- address structure:
|
-- address structure:
|
-- bit: highest -> '1': modulus
|
-- bit: highest -> '1': modulus
|
-- '0': operands
|
-- '0': operands
|
-- bits: (highest-1)-log2(width/32) -> operand_in_sel in case of highest bit = '0'
|
-- bits: (highest-1)-log2(width/32) -> operand_in_sel in case of highest bit = '0'
|
-- modulus_in_sel in case of highest bit = '1'
|
-- modulus_in_sel in case of highest bit = '1'
|
-- bits: (log2(width/32)-1)-0 -> modulus_addr / operand_addr resp.
|
-- bits: (log2(width/32)-1)-0 -> modulus_addr / operand_addr resp.
|
--
|
--
|
component operand_mem_gen is
|
component operand_mem is
|
generic(
|
generic(
|
width : integer := 1536; -- width of the operands
|
width : integer := 1536; -- width of the operands
|
nr_op : integer := 4; -- nr of operand storages, has to be greater than nr_m
|
nr_op : integer := 4; -- nr of operand storages, has to be greater than nr_m
|
nr_m : integer := 2 -- nr of modulus storages
|
nr_m : integer := 2; -- nr of modulus storages
|
|
mem_style : string := "asym"; -- xil_prim, generic, asym are valid options
|
|
device : string := "altera" -- xilinx, altera are valid options
|
);
|
);
|
port(
|
port(
|
-- system clock
|
-- system clock
|
clk : in std_logic;
|
clk : in std_logic;
|
-- data interface (plb side)
|
-- data interface (plb side)
|
| Line 757... |
Line 909... |
load_result : in std_logic;
|
load_result : in std_logic;
|
result_dest_op : in std_logic_vector(log2(nr_op)-1 downto 0);
|
result_dest_op : in std_logic_vector(log2(nr_op)-1 downto 0);
|
collision : out std_logic;
|
collision : out std_logic;
|
modulus_sel : in std_logic_vector(log2(nr_m)-1 downto 0)
|
modulus_sel : in std_logic_vector(log2(nr_m)-1 downto 0)
|
);
|
);
|
end component operand_mem_gen;
|
end component operand_mem;
|
|
|
|
|
|
|
---------------------------- TOP LEVEL -----------------------------
|
---------------------------- TOP LEVEL -----------------------------
|
|
|
--------------------------------------------------------------------
|
--------------------------------------------------------------------
|
| Line 777... |
Line 930... |
C_NR_STAGES_TOTAL : integer := 96;
|
C_NR_STAGES_TOTAL : integer := 96;
|
C_NR_STAGES_LOW : integer := 32;
|
C_NR_STAGES_LOW : integer := 32;
|
C_SPLIT_PIPELINE : boolean := true;
|
C_SPLIT_PIPELINE : boolean := true;
|
C_NR_OP : integer := 4;
|
C_NR_OP : integer := 4;
|
C_NR_M : integer := 2;
|
C_NR_M : integer := 2;
|
C_FIFO_DEPTH : integer := 32
|
C_FIFO_DEPTH : integer := 32;
|
|
C_MEM_STYLE : string := "generic"; -- xil_prim, generic, asym are valid options
|
|
C_DEVICE : string := "xilinx" -- xilinx, altera are valid options
|
);
|
);
|
port(
|
port(
|
clk : in std_logic;
|
clk : in std_logic;
|
reset : in std_logic;
|
reset : in std_logic;
|
-- operand memory interface (plb shared memory)
|
-- operand memory interface (plb shared memory)
|
write_enable : in std_logic; -- write data to operand ram
|
write_enable : in std_logic; -- write data to operand ram
|
data_in : in std_logic_vector (31 downto 0); -- operand ram data in
|
data_in : in std_logic_vector (31 downto 0); -- operand ram data in
|
rw_address : in std_logic_vector (8 downto 0); -- operand ram address bus
|
rw_address : in std_logic_vector (log2(C_NR_OP)+log2(C_NR_BITS_TOTAL/32) downto 0); -- operand ram address bus
|
data_out : out std_logic_vector (31 downto 0); -- operand ram data out
|
data_out : out std_logic_vector (31 downto 0); -- operand ram data out
|
collision : out std_logic; -- write collision
|
collision : out std_logic; -- write collision
|
-- op_sel fifo interface
|
-- op_sel fifo interface
|
fifo_din : in std_logic_vector (31 downto 0); -- exponent fifo data in
|
fifo_din : in std_logic_vector (31 downto 0); -- exponent fifo data in
|
fifo_push : in std_logic; -- push data in exponent fifo
|
fifo_push : in std_logic; -- push data in exponent fifo
|
| Line 797... |
Line 952... |
fifo_nopush : out std_logic; -- high if error during push
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fifo_nopush : out std_logic; -- high if error during push
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-- control signals
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-- control signals
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start : in std_logic; -- start multiplication/exponentiation
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start : in std_logic; -- start multiplication/exponentiation
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exp_m : in std_logic; -- single multiplication if low, exponentiation if high
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exp_m : in std_logic; -- single multiplication if low, exponentiation if high
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ready : out std_logic; -- calculations done
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ready : out std_logic; -- calculations done
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x_sel_single : in std_logic_vector (1 downto 0); -- single multiplication x operand selection
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x_sel_single : in std_logic_vector (log2(C_NR_OP)-1 downto 0); -- single multiplication x operand selection
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y_sel_single : in std_logic_vector (1 downto 0); -- single multiplication y operand selection
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y_sel_single : in std_logic_vector (log2(C_NR_OP)-1 downto 0); -- single multiplication y operand selection
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dest_op_single : in std_logic_vector (1 downto 0); -- result destination operand selection
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dest_op_single : in std_logic_vector (log2(C_NR_OP)-1 downto 0); -- result destination operand selection
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p_sel : in std_logic_vector (1 downto 0); -- pipeline part selection
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p_sel : in std_logic_vector (1 downto 0); -- pipeline part selection
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calc_time : out std_logic;
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calc_time : out std_logic;
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modulus_sel : in std_logic_vector(log2(C_NR_M)-1 downto 0)
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modulus_sel : in std_logic_vector(log2(C_NR_M)-1 downto 0) -- selects which modulus to use for multiplications
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);
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);
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end component mod_sim_exp_core;
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end component mod_sim_exp_core;
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end package mod_sim_exp_pkg;
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end package mod_sim_exp_pkg;
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