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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [mod_sim_exp_pkg.vhd] - Diff between revs 75 and 84

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Rev 75 Rev 84
Line 930... Line 930...
      C_NR_STAGES_TOTAL : integer := 96;
      C_NR_STAGES_TOTAL : integer := 96;
      C_NR_STAGES_LOW   : integer := 32;
      C_NR_STAGES_LOW   : integer := 32;
      C_SPLIT_PIPELINE  : boolean := true;
      C_SPLIT_PIPELINE  : boolean := true;
      C_FIFO_DEPTH      : integer := 32;
      C_FIFO_DEPTH      : integer := 32;
      C_MEM_STYLE       : string  := "generic"; -- xil_prim, generic, asym are valid options
      C_MEM_STYLE       : string  := "generic"; -- xil_prim, generic, asym are valid options
      C_DEVICE          : string  := "xilinx"   -- xilinx, altera are valid options
      C_FPGA_MAN        : string  := "xilinx"   -- xilinx, altera are valid options
    );
    );
    port(
    port(
      clk   : in  std_logic;
      clk   : in  std_logic;
      reset : in  std_logic;
      reset : in  std_logic;
        -- operand memory interface (plb shared memory)
        -- operand memory interface (plb shared memory)

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