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----------------------------------------------------------------------
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---- mod_sim_exp_pkg ----
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---- ----
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---- This file is part of the ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- ----
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---- Description ----
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---- Package for the Modular Simultaneous Exponentiation Core ----
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---- Project. Contains the component declarations and used ----
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---- constants. ----
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---- ----
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---- Dependencies: none ----
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---- ----
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---- Authors: ----
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---- - Geoffrey Ottoy, DraMCo research group ----
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---- - Jonas De Craene, JonasDC@opencores.org ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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package mod_sim_exp_pkg is
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package mod_sim_exp_pkg is
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component adder_n is
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-- 1-bit D flip-flop with asynchronous active high reset
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generic (
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component d_flip_flop is
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width : integer := 1536;
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block_width : integer := 8
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);
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port (
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port (
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core_clk : in std_logic;
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core_clk : in std_logic; -- clock signal
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a : in std_logic_vector((width-1) downto 0);
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reset : in std_logic; -- active high reset
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b : in std_logic_vector((width-1) downto 0);
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din : in std_logic; -- data in
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cin : in std_logic;
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dout : out std_logic -- data out
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cout : out std_logic;
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s : out std_logic_vector((width-1) downto 0)
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);
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);
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end component adder_n;
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end component d_flip_flop;
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component adder_block is
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-- 1-bit register with asynchronous reset and clock enable
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generic (
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component register_1b is
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width : integer := 32
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);
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port (
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port (
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core_clk : in std_logic;
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core_clk : in std_logic; -- clock input
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a : in std_logic_vector((width-1) downto 0);
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ce : in std_logic; -- clock enable (active high)
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b : in std_logic_vector((width-1) downto 0);
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reset : in std_logic; -- reset (active high)
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cin : in std_logic;
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din : in std_logic; -- data in
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cout : out std_logic;
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dout : out std_logic -- data out
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s : out std_logic_vector((width-1) downto 0)
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);
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);
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end component adder_block;
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end component register_1b;
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component autorun_cntrl is
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-- n-bit register with asynchronous reset and clock enable
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component register_n is
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generic(
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n : integer := 4
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);
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port (
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port (
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clk : in std_logic;
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core_clk : in std_logic; -- clock input
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reset : in std_logic;
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ce : in std_logic; -- clock enable (active high)
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start : in std_logic;
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reset : in std_logic; -- reset (active high)
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done : out std_logic;
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din : in std_logic_vector((n-1) downto 0); -- data in (n-bit)
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op_sel : out std_logic_vector (1 downto 0);
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dout : out std_logic_vector((n-1) downto 0) -- data out (n-bit)
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start_multiplier : out std_logic;
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multiplier_done : in std_logic;
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read_buffer : out std_logic;
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buffer_din : in std_logic_vector (31 downto 0);
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buffer_empty : in std_logic
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);
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);
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end component autorun_cntrl;
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end component register_n;
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-- 1-bit full adder cell
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component cell_1b_adder is
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component cell_1b_adder is
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port (
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port (
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-- input operands a, b
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a : in std_logic;
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a : in std_logic;
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mux_result : in std_logic;
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b : in std_logic;
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-- carry in, out
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cin : in std_logic;
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cin : in std_logic;
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cout : out std_logic;
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cout : out std_logic;
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-- result out
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r : out std_logic
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r : out std_logic
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);
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);
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end component cell_1b_adder;
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end component cell_1b_adder;
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-- 1-bit mux for a standard cell in the montgommery multiplier systolic array
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component cell_1b_mux is
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component cell_1b_mux is
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port (
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port (
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-- input bits
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my : in std_logic;
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my : in std_logic;
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y : in std_logic;
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y : in std_logic;
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m : in std_logic;
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m : in std_logic;
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-- selection bits
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x : in std_logic;
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x : in std_logic;
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q : in std_logic;
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q : in std_logic;
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-- mux out
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result : out std_logic
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result : out std_logic
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);
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);
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end component cell_1b_mux;
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end component cell_1b_mux;
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-- 1-bit cell for the systolic array
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component cell_1b is
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component cell_1b is
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port (
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port (
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-- operand input bits (m+y, y and m)
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my : in std_logic;
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my : in std_logic;
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y : in std_logic;
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y : in std_logic;
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m : in std_logic;
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m : in std_logic;
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-- operand x input bit and q (serial)
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x : in std_logic;
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x : in std_logic;
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q : in std_logic;
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q : in std_logic;
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-- previous result input bit
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a : in std_logic;
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a : in std_logic;
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-- carry's
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cin : in std_logic;
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cin : in std_logic;
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cout : out std_logic;
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cout : out std_logic;
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-- cell result out
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r : out std_logic
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r : out std_logic
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);
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);
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end component cell_1b;
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end component cell_1b;
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-- (width)-bit full adder block using cell_1b_adders
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-- with buffered carry out
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component adder_block is
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generic (
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width : integer := 32 --adder operand widths
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);
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port (
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-- clock input
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core_clk : in std_logic;
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-- adder input operands a, b (width)-bit
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a : in std_logic_vector((width-1) downto 0);
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b : in std_logic_vector((width-1) downto 0);
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-- carry in, out
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cin : in std_logic;
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cout : out std_logic;
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-- adder result out (width)-bit
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r : out std_logic_vector((width-1) downto 0)
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);
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end component adder_block;
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-- n-bit adder using adder blocks. works in stages, to prevent large
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-- carry propagation
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component adder_n is
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generic (
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width : integer := 1536; -- adder operands width
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block_width : integer := 8 -- adder blocks size
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);
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port (
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-- clock input
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core_clk : in std_logic;
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-- adder input operands (width)-bit
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a : in std_logic_vector((width-1) downto 0);
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b : in std_logic_vector((width-1) downto 0);
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-- carry in, out
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cin : in std_logic;
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cout : out std_logic;
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-- adder output result (width)-bit
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r : out std_logic_vector((width-1) downto 0)
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);
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end component adder_n;
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component autorun_cntrl is
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port (
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clk : in std_logic;
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reset : in std_logic;
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start : in std_logic;
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done : out std_logic;
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op_sel : out std_logic_vector (1 downto 0);
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start_multiplier : out std_logic;
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multiplier_done : in std_logic;
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read_buffer : out std_logic;
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buffer_din : in std_logic_vector (31 downto 0);
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buffer_empty : in std_logic
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);
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end component autorun_cntrl;
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component counter_sync is
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component counter_sync is
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generic(
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generic(
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max_value : integer := 1024
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max_value : integer := 1024
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);
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);
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port(
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port(
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reset : in std_logic;
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reset : in std_logic;
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overflow : out std_logic
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overflow : out std_logic
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);
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);
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end component counter_sync;
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end component counter_sync;
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component d_flip_flop is
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port(
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core_clk : in std_logic;
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reset : in std_logic;
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din : in std_logic;
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dout : out std_logic
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);
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end component d_flip_flop;
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component fifo_primitive is
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component fifo_primitive is
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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din : in std_logic_vector (31 downto 0);
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din : in std_logic_vector (31 downto 0);
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dout : out std_logic_vector (31 downto 0);
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dout : out std_logic_vector (31 downto 0);
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dina : in std_logic_vector(31 downto 0);
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dina : in std_logic_vector(31 downto 0);
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douta : out std_logic_vector(511 downto 0)
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douta : out std_logic_vector(511 downto 0)
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);
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);
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end component operands_sp;
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end component operands_sp;
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component register_1b is
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port(
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core_clk : in std_logic;
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ce : in std_logic;
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reset : in std_logic;
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din : in std_logic;
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dout : out std_logic
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);
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end component register_1b;
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component register_n is
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generic(
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n : integer := 4
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);
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port(
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core_clk : in std_logic;
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ce : in std_logic;
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reset : in std_logic;
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din : in std_logic_vector((n-1) downto 0);
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dout : out std_logic_vector((n-1) downto 0)
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);
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end component register_n;
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component standard_cell_block is
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component standard_cell_block is
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generic (
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generic (
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width : integer := 16
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width : integer := 16
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);
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);
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port (
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port (
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