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https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [modulus_ram_asym.vhd] - Diff between revs 81 and 83
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| Rev 81 |
Rev 83 |
| Line 98... |
Line 98... |
single_block : if (width <= RAMblock_maxwidth) generate
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single_block : if (width <= RAMblock_maxwidth) generate
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signal waddr : std_logic_vector(log2((width*depth)/32)-1 downto 0);
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signal waddr : std_logic_vector(log2((width*depth)/32)-1 downto 0);
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begin
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begin
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waddr <= modulus_in_sel & modulus_addr;
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waddr <= modulus_in_sel & modulus_addr;
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|
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ramblock: entity mod_sim_exp.dpramblock_asym
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ramblock: dpramblock_asym
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generic map(
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generic map(
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width => width,
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width => width,
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depth => depth,
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depth => depth,
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device => device
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device => device
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)
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)
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| Line 160... |
Line 160... |
signal waddr_part : std_logic_vector(log2(RAMblock_part_width*depth/32)-1 downto 0);
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signal waddr_part : std_logic_vector(log2(RAMblock_part_width*depth/32)-1 downto 0);
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signal we_part : std_logic;
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signal we_part : std_logic;
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begin
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begin
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-- write port signal
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-- write port signal
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waddr_part <= modulus_in_sel & modulus_addr(log2(RAMblock_part_width/32)-1 downto 0);
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waddr_part <= modulus_in_sel & modulus_addr(log2(RAMblock_part_width/32)-1 downto 0);
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ramblock_part : entity mod_sim_exp.dpramblock_asym
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ramblock_part : dpramblock_asym
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generic map(
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generic map(
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width => RAMblock_part_width,
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width => RAMblock_part_width,
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depth => depth,
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depth => depth,
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device => device
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device => device
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)
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)
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