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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [modulus_ram_asym.vhd] - Diff between revs 81 and 83

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Rev 81 Rev 83
Line 98... Line 98...
  single_block : if (width <= RAMblock_maxwidth) generate
  single_block : if (width <= RAMblock_maxwidth) generate
    signal waddr : std_logic_vector(log2((width*depth)/32)-1 downto 0);
    signal waddr : std_logic_vector(log2((width*depth)/32)-1 downto 0);
  begin
  begin
    waddr <= modulus_in_sel & modulus_addr;
    waddr <= modulus_in_sel & modulus_addr;
 
 
    ramblock: entity mod_sim_exp.dpramblock_asym
    ramblock: dpramblock_asym
    generic map(
    generic map(
      width => width,
      width => width,
      depth => depth,
      depth => depth,
      device  => device
      device  => device
    )
    )
Line 160... Line 160...
        signal waddr_part : std_logic_vector(log2(RAMblock_part_width*depth/32)-1 downto 0);
        signal waddr_part : std_logic_vector(log2(RAMblock_part_width*depth/32)-1 downto 0);
        signal we_part    : std_logic;
        signal we_part    : std_logic;
      begin
      begin
        -- write port signal
        -- write port signal
        waddr_part <= modulus_in_sel & modulus_addr(log2(RAMblock_part_width/32)-1 downto 0);
        waddr_part <= modulus_in_sel & modulus_addr(log2(RAMblock_part_width/32)-1 downto 0);
        ramblock_part : entity mod_sim_exp.dpramblock_asym
        ramblock_part : dpramblock_asym
        generic map(
        generic map(
          width  => RAMblock_part_width,
          width  => RAMblock_part_width,
          depth  => depth,
          depth  => depth,
          device => device
          device => device
        )
        )

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