----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- modulus_ram_asym ----
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---- modulus_ram_asym ----
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---- ----
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---- ----
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---- This file is part of the ----
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---- This file is part of the ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- ----
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---- ----
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---- Description ----
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---- Description ----
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---- BRAM memory and logic to store the modulus, due to the ----
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---- BRAM memory and logic to store the modulus, due to the ----
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---- achitecture, a minimum depth of 2 is needed for this ----
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---- achitecture, a minimum depth of 2 is needed for this ----
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---- module to be inferred into blockram, this version is ----
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---- module to be inferred into blockram, this version is ----
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---- slightly more performant than modulus_ram_gen and uses ----
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---- slightly more performant than modulus_ram_gen and uses ----
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---- less resources. but does not work on every fpga, only ----
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---- less resources. but does not work on every fpga, only ----
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---- the ones that support asymmetric rams. ----
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---- the ones that support asymmetric rams. ----
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---- ----
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---- ----
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---- Dependencies: ----
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---- Dependencies: ----
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---- - dpramblock_asym ----
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---- - dpramblock_asym ----
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---- ----
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---- ----
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---- Authors: ----
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---- Authors: ----
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---- - Geoffrey Ottoy, DraMCo research group ----
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---- - Geoffrey Ottoy, DraMCo research group ----
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---- - Jonas De Craene, JonasDC@opencores.org ----
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---- - Jonas De Craene, JonasDC@opencores.org ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- ----
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---- ----
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
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---- ----
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---- ----
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---- This source file may be used and distributed without ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- later version. ----
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---- ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- details. ----
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---- ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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library mod_sim_exp;
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library mod_sim_exp;
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use mod_sim_exp.std_functions.all;
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use mod_sim_exp.std_functions.all;
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use mod_sim_exp.mod_sim_exp_pkg.all;
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use mod_sim_exp.mod_sim_exp_pkg.all;
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-- structural description of a RAM to hold the modulus, with
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-- structural description of a RAM to hold the modulus, with
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-- adjustable width (64, 128, 256, 512, 576, 640,..) and depth(nr of moduluses)
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-- adjustable width (64, 128, 256, 512, 576, 640,..) and depth(nr of moduluses)
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-- formula for available widths: (i*512+(0 or 64 or 128 or 256)) (i=integer number)
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-- formula for available widths: (i*512+(0 or 64 or 128 or 256)) (i=integer number)
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--
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--
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entity modulus_ram_asym is
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entity modulus_ram_asym is
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generic(
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generic(
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width : integer := 1536; -- must be a multiple of 32
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width : integer := 1536; -- must be a multiple of 32
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depth : integer := 2; -- nr of moduluses
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depth : integer := 2; -- nr of moduluses
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device : string := "xilinx"
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device : string := "xilinx"
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);
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);
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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-- bus side
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-- bus side
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write_modulus : in std_logic; -- write enable
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write_modulus : in std_logic; -- write enable
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modulus_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- modulus operand to write to
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modulus_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- modulus operand to write to
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modulus_addr : in std_logic_vector(log2((width)/32)-1 downto 0); -- modulus word(32-bit) address
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modulus_addr : in std_logic_vector(log2((width)/32)-1 downto 0); -- modulus word(32-bit) address
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modulus_in : in std_logic_vector(31 downto 0); -- modulus word data in
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modulus_in : in std_logic_vector(31 downto 0); -- modulus word data in
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modulus_sel : in std_logic_vector(log2(depth)-1 downto 0); -- selects the modulus to use for multiplications
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modulus_sel : in std_logic_vector(log2(depth)-1 downto 0); -- selects the modulus to use for multiplications
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-- multiplier side
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-- multiplier side
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modulus_out : out std_logic_vector(width-1 downto 0)
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modulus_out : out std_logic_vector(width-1 downto 0)
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);
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);
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end modulus_ram_asym;
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end modulus_ram_asym;
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architecture structural of modulus_ram_asym is
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architecture structural of modulus_ram_asym is
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-- constants
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-- constants
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constant RAMblock_maxwidth : integer := 512;
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constant RAMblock_maxwidth : integer := 512;
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constant nrRAMblocks_full : integer := width/RAMblock_maxwidth;
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constant nrRAMblocks_full : integer := width/RAMblock_maxwidth;
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constant RAMblock_part : integer := width rem RAMblock_maxwidth;
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constant RAMblock_part : integer := width rem RAMblock_maxwidth;
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constant RAMblock_part_width : integer := width-(nrRAMblocks_full*RAMblock_maxwidth);
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constant RAMblock_part_width : integer := width-(nrRAMblocks_full*RAMblock_maxwidth);
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constant RAMselect_aw : integer := log2(width/32)-log2(nrRAMblocks_full/32);
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constant RAMselect_aw : integer := log2(width/32)-log2(nrRAMblocks_full/32);
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begin
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begin
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-- generate (width/512) ramblocks with a given depth
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-- generate (width/512) ramblocks with a given depth
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-- these rams are tyed together to form the following structure
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-- these rams are tyed together to form the following structure
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-- dual port ram:
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-- dual port ram:
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-- - PORT A : 32-bit write
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-- - PORT A : 32-bit write
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-- - PORT B : (width)-bit read
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-- - PORT B : (width)-bit read
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--
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--
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single_block : if (width <= RAMblock_maxwidth) generate
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single_block : if (width <= RAMblock_maxwidth) generate
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signal waddr : std_logic_vector(log2((width*depth)/32)-1 downto 0);
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signal waddr : std_logic_vector(log2((width*depth)/32)-1 downto 0);
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begin
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begin
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waddr <= modulus_in_sel & modulus_addr;
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waddr <= modulus_in_sel & modulus_addr;
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ramblock: entity mod_sim_exp.dpramblock_asym
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ramblock: dpramblock_asym
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generic map(
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generic map(
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width => width,
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width => width,
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depth => depth,
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depth => depth,
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device => device
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device => device
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)
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)
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port map(
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port map(
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clk => clk,
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clk => clk,
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-- write port
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-- write port
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waddr => waddr,
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waddr => waddr,
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we => write_modulus,
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we => write_modulus,
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din => modulus_in,
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din => modulus_in,
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-- read port
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-- read port
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raddr => modulus_sel,
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raddr => modulus_sel,
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dout => modulus_out
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dout => modulus_out
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);
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);
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end generate;
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end generate;
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multiple_full_blocks : if (width > RAMblock_maxwidth) generate
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multiple_full_blocks : if (width > RAMblock_maxwidth) generate
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-- signals for multiple blocks
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-- signals for multiple blocks
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signal waddr : std_logic_vector(log2(RAMblock_maxwidth*depth/32)-1 downto 0);
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signal waddr : std_logic_vector(log2(RAMblock_maxwidth*depth/32)-1 downto 0);
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signal we_RAM : std_logic_vector(nrRAMblocks_full-1 downto 0);
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signal we_RAM : std_logic_vector(nrRAMblocks_full-1 downto 0);
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begin
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begin
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ramblocks_full : for i in 0 to nrRAMblocks_full generate
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ramblocks_full : for i in 0 to nrRAMblocks_full generate
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-- write port signal
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-- write port signal
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waddr <= modulus_in_sel & modulus_addr(log2(RAMblock_maxwidth/32)-1 downto 0);
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waddr <= modulus_in_sel & modulus_addr(log2(RAMblock_maxwidth/32)-1 downto 0);
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full_ones : if (i < nrRAMblocks_full) generate
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full_ones : if (i < nrRAMblocks_full) generate
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ramblock_full : dpramblock_asym
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ramblock_full : dpramblock_asym
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generic map(
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generic map(
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width => RAMblock_maxwidth,
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width => RAMblock_maxwidth,
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depth => depth,
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depth => depth,
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device => device
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device => device
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)
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)
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port map(
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port map(
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clk => clk,
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clk => clk,
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-- write port
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-- write port
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waddr => waddr,
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waddr => waddr,
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we => we_RAM(i),
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we => we_RAM(i),
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din => modulus_in,
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din => modulus_in,
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-- read port
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-- read port
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raddr => modulus_sel,
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raddr => modulus_sel,
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dout => modulus_out((i+1)*RAMblock_maxwidth-1 downto i*RAMblock_maxwidth)
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dout => modulus_out((i+1)*RAMblock_maxwidth-1 downto i*RAMblock_maxwidth)
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);
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);
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-- we
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-- we
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process (write_modulus, modulus_addr)
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process (write_modulus, modulus_addr)
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begin
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begin
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if modulus_addr(log2(width/32)-1 downto log2(RAMblock_maxwidth/32)) = conv_std_logic_vector(i,RAMselect_aw) then
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if modulus_addr(log2(width/32)-1 downto log2(RAMblock_maxwidth/32)) = conv_std_logic_vector(i,RAMselect_aw) then
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we_RAM(i) <= write_modulus;
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we_RAM(i) <= write_modulus;
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else
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else
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we_RAM(i) <= '0';
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we_RAM(i) <= '0';
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end if;
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end if;
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end process;
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end process;
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end generate; -- end of if generate for full blocks
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end generate; -- end of if generate for full blocks
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optional_part : if (i = nrRAMblocks_full) and (RAMblock_part /= 0) generate
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optional_part : if (i = nrRAMblocks_full) and (RAMblock_part /= 0) generate
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-- signals for optional part
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-- signals for optional part
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signal waddr_part : std_logic_vector(log2(RAMblock_part_width*depth/32)-1 downto 0);
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signal waddr_part : std_logic_vector(log2(RAMblock_part_width*depth/32)-1 downto 0);
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signal we_part : std_logic;
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signal we_part : std_logic;
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begin
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begin
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-- write port signal
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-- write port signal
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waddr_part <= modulus_in_sel & modulus_addr(log2(RAMblock_part_width/32)-1 downto 0);
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waddr_part <= modulus_in_sel & modulus_addr(log2(RAMblock_part_width/32)-1 downto 0);
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ramblock_part : entity mod_sim_exp.dpramblock_asym
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ramblock_part : dpramblock_asym
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generic map(
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generic map(
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width => RAMblock_part_width,
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width => RAMblock_part_width,
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depth => depth,
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depth => depth,
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device => device
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device => device
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)
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)
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port map(
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port map(
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clk => clk,
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clk => clk,
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-- write port
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-- write port
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waddr => waddr_part,
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waddr => waddr_part,
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we => we_part,
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we => we_part,
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din => modulus_in,
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din => modulus_in,
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-- read port
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-- read port
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raddr => modulus_sel,
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raddr => modulus_sel,
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dout => modulus_out(width-1 downto i*RAMblock_maxwidth)
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dout => modulus_out(width-1 downto i*RAMblock_maxwidth)
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);
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);
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-- we_part
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-- we_part
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process (write_modulus, modulus_addr)
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process (write_modulus, modulus_addr)
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begin
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begin
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if modulus_addr(log2(width/32)-1 downto log2(RAMblock_maxwidth/32)) = conv_std_logic_vector(i,RAMselect_aw) then
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if modulus_addr(log2(width/32)-1 downto log2(RAMblock_maxwidth/32)) = conv_std_logic_vector(i,RAMselect_aw) then
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we_part <= write_modulus;
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we_part <= write_modulus;
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else
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else
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we_part <= '0';
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we_part <= '0';
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end if;
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end if;
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end process;
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end process;
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end generate;-- end of if generate for part block
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end generate;-- end of if generate for part block
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end generate;-- end of for generate
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end generate;-- end of for generate
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end generate;-- end of if generate for multiple blocks
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end generate;-- end of if generate for multiple blocks
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end structural;
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end structural;
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