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------------------------------------------------------------------------------------ 
----------------------------------------------------------------------  
--                      
----  mont_ctrl                                                   ---- 
-- Geoffrey Ottoy - DraMCo research group
----                                                              ---- 
--
----  This file is part of the                                    ----
-- Module Name: mont_ctrl.vhd / entity mont_ctrl
----    Modular Simultaneous Exponentiation Core project          ---- 
-- 
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
-- Last Modified:       25/04/2012 
----                                                              ---- 
-- 
----  Description                                                 ---- 
-- Description:         control unit for a pipelined montgomery multiplier, with split
----    control unit for a pipelined montgomery multiplier, with  ----
--                pipeline operation and "auto-run" support
----    split pipeline operation and "auto-run" support           ----
--
----                                                              ----
--
----  Dependencies:                                               ----
-- Dependencies:        autorun_cntrl
----    - autorun_cntrl                                           ----
--
----                                                              ----
-- Revision:
----  Authors:                                                    ----
-- Revision 2.00 - Added autorun_control_logic
----      - Geoffrey Ottoy, DraMCo research group                 ----
--      Revision 1.00 - Architecture with support for single multiplication
----      - Jonas De Craene, JonasDC@opencores.org                ---- 
--      Revision 0.01 - File Created
----                                                              ---- 
--
---------------------------------------------------------------------- 
--
----                                                              ---- 
------------------------------------------------------------------------------------
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
--
----                                                              ---- 
-- NOTICE:
---- This source file may be used and distributed without         ---- 
--
---- restriction provided that this copyright statement is not    ---- 
-- Copyright DraMCo research group. 2011. This code may be contain portions patented
---- removed from the file and that any derivative work contains  ---- 
-- by other third parties!
---- the original copyright notice and the associated disclaimer. ---- 
--
----                                                              ---- 
------------------------------------------------------------------------------------
---- This source file is free software; you can redistribute it   ---- 
library IEEE;
---- and/or modify it under the terms of the GNU Lesser General   ---- 
use IEEE.STD_LOGIC_1164.ALL;
---- Public License as published by the Free Software Foundation; ---- 
use IEEE.STD_LOGIC_ARITH.ALL;
---- either version 2.1 of the License, or (at your option) any   ---- 
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- later version.                                               ---- 
 
----                                                              ---- 
---- Uncomment the following library declaration if instantiating
---- This source is distributed in the hope that it will be       ---- 
---- any Xilinx primitives in this code.
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
--library UNISIM;
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
--use UNISIM.VComponents.all;
---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
 
---- details.                                                     ---- 
 
----                                                              ---- 
 
---- You should have received a copy of the GNU Lesser General    ---- 
 
---- Public License along with this source; if not, download it   ---- 
 
---- from http://www.opencores.org/lgpl.shtml                     ---- 
 
----                                                              ---- 
 
----------------------------------------------------------------------
 
 
 
library ieee;
 
use ieee.std_logic_1164.all;
 
use ieee.std_logic_arith.all;
 
use ieee.std_logic_unsigned.all;
 
 
 
library mod_sim_exp;
 
use mod_sim_exp.mod_sim_exp_pkg.all;
 
 
 
 
entity mont_ctrl is
entity mont_ctrl is
  port ( clk : in std_logic; --v
  port (
         reset : in std_logic; --v
    clk   : in std_logic;
 
    reset : in std_logic;
                        -- bus side
                        -- bus side
                        start : in std_logic; --v
    start           : in std_logic;
         --p_sel : in std_logic_vector(1 downto 0);
    x_sel_single    : in std_logic_vector(1 downto 0);
         x_sel_single : in std_logic_vector(1 downto 0); --v
    y_sel_single    : in std_logic_vector(1 downto 0);
         y_sel_single : in std_logic_vector(1 downto 0); --v
 
                        run_auto : in std_logic;
                        run_auto : in std_logic;
         op_buffer_empty : in std_logic;
         op_buffer_empty : in std_logic;
         op_sel_buffer : in std_logic_vector(31 downto 0);
         op_sel_buffer : in std_logic_vector(31 downto 0);
                        read_buffer : out std_logic;
                        read_buffer : out std_logic;
                        buffer_noread : in std_logic;
                        buffer_noread : in std_logic;
                        done : out std_logic;
                        done : out std_logic;
         calc_time : out std_logic; -- v
    calc_time       : out std_logic;
                        -- multiplier side
                        -- multiplier side
                        op_sel : out std_logic_vector(1 downto 0); --v
    op_sel           : out std_logic_vector(1 downto 0);
                        load_x : out std_logic;  -- v
    load_x           : out std_logic;
                        load_result : out std_logic; --v 
    load_result      : out std_logic;
                        start_multiplier : out std_logic; -- v
    start_multiplier : out std_logic;
                        multiplier_ready : in std_logic
                        multiplier_ready : in std_logic
 
 
  );
  );
end mont_ctrl;
end mont_ctrl;
 
 
 
 
architecture Behavioral of mont_ctrl is
architecture Behavioral of mont_ctrl is
        signal start_delayed_i : std_logic; -- delayed version of start input
        signal start_delayed_i : std_logic; -- delayed version of start input
        signal start_pulse_i : std_logic;
        signal start_pulse_i : std_logic;
        signal auto_start_pulse_i : std_logic;
        signal auto_start_pulse_i : std_logic;
        signal start_multiplier_i : std_logic;
        signal start_multiplier_i : std_logic;
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        signal start_autorun_cycle_1_i : std_logic;
        signal start_autorun_cycle_1_i : std_logic;
        signal autorun_counter_i : std_logic_vector(1 downto 0);
        signal autorun_counter_i : std_logic_vector(1 downto 0);
        signal part_counter_i : std_logic_vector(2 downto 0);
        signal part_counter_i : std_logic_vector(2 downto 0);
        signal auto_multiplier_done_i : std_logic;
        signal auto_multiplier_done_i : std_logic;
 
 
        COMPONENT autorun_cntrl
 
        PORT(
 
                clk : IN std_logic;
 
                reset : IN std_logic;
 
                start : IN std_logic;
 
                multiplier_done : IN std_logic;
 
                buffer_din : IN std_logic_vector(31 downto 0);
 
                buffer_empty : IN std_logic;
 
                done : OUT std_logic;
 
                op_sel : OUT std_logic_vector(1 downto 0);
 
                start_multiplier : OUT std_logic;
 
                read_buffer : OUT std_logic
 
                );
 
        END COMPONENT;
 
begin
begin
 
 
        -----------------------------------------------------------------------------------
        -----------------------------------------------------------------------------------
        -- Processes related to starting and stopping the multiplier
        -- Processes related to starting and stopping the multiplier
        -----------------------------------------------------------------------------------
        -----------------------------------------------------------------------------------
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        begin
        begin
                if rising_edge(clk) then
                if rising_edge(clk) then
                        start_delayed_i <= start;
                        start_delayed_i <= start;
                end if;
                end if;
        end process START_PULSE_PROC;
        end process START_PULSE_PROC;
        --start_pulse_i <= store_autorun_i and (not run_auto_i);
 
        start_pulse_i <= start and (not start_delayed_i);
        start_pulse_i <= start and (not start_delayed_i);
        single_start_pulse_i <= start_pulse_i and (not run_auto_i);
        single_start_pulse_i <= start_pulse_i and (not run_auto_i);
        --store_autorun_i <= (start and (not start_delayed_i));
 
        --start_auto_i <= store_autorun_i and run_auto_i;
 
        start_auto_i <= start_pulse_i and run_auto_i;
        start_auto_i <= start_pulse_i and run_auto_i;
 
 
        -- to start the multiplier we first need to select the y_operand and
        -- to start the multiplier we first need to select the y_operand and
        -- clock it in the y_register
        -- clock it in the y_register
        -- the we select the x_operand and start the multiplier
        -- the we select the x_operand and start the multiplier
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--                              run_auto_stored_i <= run_auto_stored_i;
--                              run_auto_stored_i <= run_auto_stored_i;
--                      end if;
--                      end if;
--              end if;
--              end if;
--      end process STORE_AUTORUN_PROC;
--      end process STORE_AUTORUN_PROC;
        run_auto_i <= run_auto;
        run_auto_i <= run_auto;
        --run_auto_i <= run_auto or run_auto_stored_i;
 
 
 
 
 
        -- multiplier_ready is only passed to autorun control when in autorun mode
        -- multiplier_ready is only passed to autorun control when in autorun mode
        auto_multiplier_done_i <= (multiplier_ready and run_auto_i);
        auto_multiplier_done_i <= (multiplier_ready and run_auto_i);
        autorun_control_logic: autorun_cntrl PORT MAP(
 
 
  autorun_control_logic : autorun_cntrl port map(
                clk => clk,
                clk => clk,
                reset => reset,
                reset => reset,
                start => start_auto_i,
                start => start_auto_i,
                done => auto_done_i,
                done => auto_done_i,
                op_sel => x_sel_buffer_i,
                op_sel => x_sel_buffer_i,
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                multiplier_done => auto_multiplier_done_i,
                multiplier_done => auto_multiplier_done_i,
                read_buffer => read_buffer,
                read_buffer => read_buffer,
                buffer_din => op_sel_buffer,
                buffer_din => op_sel_buffer,
                buffer_empty => op_buffer_empty
                buffer_empty => op_buffer_empty
        );
        );
end Behavioral;
 
 
 
 
end Behavioral;
 
 
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