------------------------------------------------------------------------------------
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----------------------------------------------------------------------
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--
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---- mont_ctrl ----
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-- Geoffrey Ottoy - DraMCo research group
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---- ----
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--
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---- This file is part of the ----
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-- Module Name: mont_ctrl.vhd / entity mont_ctrl
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---- Modular Simultaneous Exponentiation Core project ----
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--
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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-- Last Modified: 25/04/2012
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---- ----
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--
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---- Description ----
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-- Description: control unit for a pipelined montgomery multiplier, with split
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---- control unit for a pipelined montgomery multiplier, with ----
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-- pipeline operation and "auto-run" support
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---- split pipeline operation and "auto-run" support ----
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--
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---- ----
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--
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---- Dependencies: ----
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-- Dependencies: autorun_cntrl
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---- - autorun_cntrl ----
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--
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---- ----
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-- Revision:
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---- Authors: ----
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-- Revision 2.00 - Added autorun_control_logic
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---- - Geoffrey Ottoy, DraMCo research group ----
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-- Revision 1.00 - Architecture with support for single multiplication
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---- - Jonas De Craene, JonasDC@opencores.org ----
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-- Revision 0.01 - File Created
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---- ----
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--
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----------------------------------------------------------------------
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--
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---- ----
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------------------------------------------------------------------------------------
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
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--
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---- ----
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-- NOTICE:
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---- This source file may be used and distributed without ----
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--
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---- restriction provided that this copyright statement is not ----
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-- Copyright DraMCo research group. 2011. This code may be contain portions patented
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---- removed from the file and that any derivative work contains ----
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-- by other third parties!
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---- the original copyright notice and the associated disclaimer. ----
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--
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---- ----
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------------------------------------------------------------------------------------
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---- This source file is free software; you can redistribute it ----
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library IEEE;
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---- and/or modify it under the terms of the GNU Lesser General ----
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use IEEE.STD_LOGIC_1164.ALL;
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---- Public License as published by the Free Software Foundation; ----
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use IEEE.STD_LOGIC_ARITH.ALL;
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---- either version 2.1 of the License, or (at your option) any ----
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- later version. ----
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---- ----
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---- Uncomment the following library declaration if instantiating
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---- This source is distributed in the hope that it will be ----
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---- any Xilinx primitives in this code.
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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--library UNISIM;
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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--use UNISIM.VComponents.all;
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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library mod_sim_exp;
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use mod_sim_exp.mod_sim_exp_pkg.all;
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entity mont_ctrl is
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entity mont_ctrl is
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port ( clk : in std_logic; --v
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port (
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reset : in std_logic; --v
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clk : in std_logic;
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reset : in std_logic;
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-- bus side
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-- bus side
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start : in std_logic; --v
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start : in std_logic;
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--p_sel : in std_logic_vector(1 downto 0);
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x_sel_single : in std_logic_vector(1 downto 0);
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x_sel_single : in std_logic_vector(1 downto 0); --v
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y_sel_single : in std_logic_vector(1 downto 0);
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y_sel_single : in std_logic_vector(1 downto 0); --v
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run_auto : in std_logic;
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run_auto : in std_logic;
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op_buffer_empty : in std_logic;
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op_buffer_empty : in std_logic;
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op_sel_buffer : in std_logic_vector(31 downto 0);
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op_sel_buffer : in std_logic_vector(31 downto 0);
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read_buffer : out std_logic;
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read_buffer : out std_logic;
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buffer_noread : in std_logic;
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buffer_noread : in std_logic;
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done : out std_logic;
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done : out std_logic;
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calc_time : out std_logic; -- v
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calc_time : out std_logic;
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-- multiplier side
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-- multiplier side
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op_sel : out std_logic_vector(1 downto 0); --v
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op_sel : out std_logic_vector(1 downto 0);
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load_x : out std_logic; -- v
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load_x : out std_logic;
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load_result : out std_logic; --v
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load_result : out std_logic;
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start_multiplier : out std_logic; -- v
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start_multiplier : out std_logic;
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multiplier_ready : in std_logic
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multiplier_ready : in std_logic
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);
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);
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end mont_ctrl;
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end mont_ctrl;
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architecture Behavioral of mont_ctrl is
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architecture Behavioral of mont_ctrl is
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signal start_delayed_i : std_logic; -- delayed version of start input
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signal start_delayed_i : std_logic; -- delayed version of start input
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signal start_pulse_i : std_logic;
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signal start_pulse_i : std_logic;
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signal auto_start_pulse_i : std_logic;
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signal auto_start_pulse_i : std_logic;
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signal start_multiplier_i : std_logic;
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signal start_multiplier_i : std_logic;
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signal start_up_counter_i : std_logic_vector(2 downto 0):= "100"; -- used in op_sel at multiplier start
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signal start_up_counter_i : std_logic_vector(2 downto 0) := "100"; -- used in op_sel at multiplier start
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signal auto_start_i : std_logic := '0';
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signal auto_start_i : std_logic := '0';
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signal store_autorun_i : std_logic;
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signal store_autorun_i : std_logic;
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signal run_auto_i : std_logic;
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signal run_auto_i : std_logic;
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signal run_auto_stored_i : std_logic := '0';
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signal run_auto_stored_i : std_logic := '0';
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signal single_start_pulse_i : std_logic;
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signal single_start_pulse_i : std_logic;
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signal calc_time_i : std_logic; -- high ('1') during multiplication
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signal calc_time_i : std_logic; -- high ('1') during multiplication
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signal x_sel_i : std_logic_vector(1 downto 0); -- the operand used as x input
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signal x_sel_i : std_logic_vector(1 downto 0); -- the operand used as x input
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signal y_sel_i : std_logic_vector(1 downto 0); -- the operand used as y input
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signal y_sel_i : std_logic_vector(1 downto 0); -- the operand used as y input
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signal x_sel_buffer_i : std_logic_vector(1 downto 0); -- x operand as specified by fifo buffer (autorun)
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signal x_sel_buffer_i : std_logic_vector(1 downto 0); -- x operand as specified by fifo buffer (autorun)
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signal auto_done_i : std_logic;
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signal auto_done_i : std_logic;
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signal start_auto_i : std_logic;
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signal start_auto_i : std_logic;
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signal new_buf_part_i : std_logic;
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signal new_buf_part_i : std_logic;
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signal new_buf_word_i : std_logic;
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signal new_buf_word_i : std_logic;
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signal buf_part_i : std_logic_vector(3 downto 0);
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signal buf_part_i : std_logic_vector(3 downto 0);
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signal pop_i : std_logic;
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signal pop_i : std_logic;
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signal start_autorun_cycle_i : std_logic;
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signal start_autorun_cycle_i : std_logic;
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signal start_autorun_cycle_1_i : std_logic;
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signal start_autorun_cycle_1_i : std_logic;
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signal autorun_counter_i : std_logic_vector(1 downto 0);
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signal autorun_counter_i : std_logic_vector(1 downto 0);
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signal part_counter_i : std_logic_vector(2 downto 0);
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signal part_counter_i : std_logic_vector(2 downto 0);
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signal auto_multiplier_done_i : std_logic;
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signal auto_multiplier_done_i : std_logic;
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COMPONENT autorun_cntrl
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PORT(
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clk : IN std_logic;
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reset : IN std_logic;
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start : IN std_logic;
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multiplier_done : IN std_logic;
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buffer_din : IN std_logic_vector(31 downto 0);
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buffer_empty : IN std_logic;
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done : OUT std_logic;
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op_sel : OUT std_logic_vector(1 downto 0);
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start_multiplier : OUT std_logic;
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read_buffer : OUT std_logic
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);
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END COMPONENT;
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begin
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begin
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-----------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------
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-- Processes related to starting and stopping the multiplier
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-- Processes related to starting and stopping the multiplier
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-----------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------
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-- generate a start pulse (duration 1 clock cycle) based on ext. start sig
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-- generate a start pulse (duration 1 clock cycle) based on ext. start sig
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START_PULSE_PROC: process(clk)
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START_PULSE_PROC: process(clk)
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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start_delayed_i <= start;
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start_delayed_i <= start;
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end if;
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end if;
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end process START_PULSE_PROC;
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end process START_PULSE_PROC;
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--start_pulse_i <= store_autorun_i and (not run_auto_i);
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start_pulse_i <= start and (not start_delayed_i);
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start_pulse_i <= start and (not start_delayed_i);
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single_start_pulse_i <= start_pulse_i and (not run_auto_i);
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single_start_pulse_i <= start_pulse_i and (not run_auto_i);
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--store_autorun_i <= (start and (not start_delayed_i));
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--start_auto_i <= store_autorun_i and run_auto_i;
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start_auto_i <= start_pulse_i and run_auto_i;
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start_auto_i <= start_pulse_i and run_auto_i;
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-- to start the multiplier we first need to select the y_operand and
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-- to start the multiplier we first need to select the y_operand and
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-- clock it in the y_register
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-- clock it in the y_register
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-- the we select the x_operand and start the multiplier
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-- the we select the x_operand and start the multiplier
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START_MULT_PROC: process(clk, reset)
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START_MULT_PROC: process(clk, reset)
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begin
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begin
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if reset = '1' then
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if reset = '1' then
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start_up_counter_i <= "100";
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start_up_counter_i <= "100";
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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if start_pulse_i = '1' or auto_start_pulse_i = '1' then
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if start_pulse_i = '1' or auto_start_pulse_i = '1' then
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start_up_counter_i <= "000";
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start_up_counter_i <= "000";
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elsif start_up_counter_i(2) /= '1' then
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elsif start_up_counter_i(2) /= '1' then
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start_up_counter_i <= start_up_counter_i + '1';
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start_up_counter_i <= start_up_counter_i + '1';
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else
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else
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start_up_counter_i <= "100";
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start_up_counter_i <= "100";
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end if;
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end if;
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else
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else
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start_up_counter_i <= start_up_counter_i;
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start_up_counter_i <= start_up_counter_i;
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end if;
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end if;
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end process;
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end process;
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-- select operands (autorun/single run)
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-- select operands (autorun/single run)
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x_sel_i <= x_sel_buffer_i when (run_auto_i = '1') else x_sel_single;
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x_sel_i <= x_sel_buffer_i when (run_auto_i = '1') else x_sel_single;
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y_sel_i <= "11" when (run_auto_i = '1') else y_sel_single; -- y is operand3 in auto mode
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y_sel_i <= "11" when (run_auto_i = '1') else y_sel_single; -- y is operand3 in auto mode
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-- clock operands to operand_mem output (first y, then x)
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-- clock operands to operand_mem output (first y, then x)
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with start_up_counter_i(2 downto 1) select
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with start_up_counter_i(2 downto 1) select
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op_sel <= y_sel_i when "00",
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op_sel <= y_sel_i when "00",
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x_sel_i when others;
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x_sel_i when others;
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load_x <= start_up_counter_i(0) and (not start_up_counter_i(1));
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load_x <= start_up_counter_i(0) and (not start_up_counter_i(1));
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-- start multiplier
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-- start multiplier
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start_multiplier_i <= start_up_counter_i(1) and start_up_counter_i(0);
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start_multiplier_i <= start_up_counter_i(1) and start_up_counter_i(0);
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start_multiplier <= start_multiplier_i;
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start_multiplier <= start_multiplier_i;
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-- signal calc time is high during multiplication
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-- signal calc time is high during multiplication
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CALC_TIME_PROC: process(clk, reset)
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CALC_TIME_PROC: process(clk, reset)
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begin
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begin
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if reset = '1' then
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if reset = '1' then
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calc_time_i <= '0';
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calc_time_i <= '0';
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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if start_multiplier_i = '1' then
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if start_multiplier_i = '1' then
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calc_time_i <= '1';
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calc_time_i <= '1';
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elsif multiplier_ready = '1' then
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elsif multiplier_ready = '1' then
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calc_time_i <= '0';
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calc_time_i <= '0';
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else
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else
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calc_time_i <= calc_time_i;
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calc_time_i <= calc_time_i;
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end if;
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end if;
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else
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else
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calc_time_i <= calc_time_i;
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calc_time_i <= calc_time_i;
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end if;
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end if;
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end process CALC_TIME_PROC;
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end process CALC_TIME_PROC;
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calc_time <= calc_time_i;
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calc_time <= calc_time_i;
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-- what happens when a multiplication has finished
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-- what happens when a multiplication has finished
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load_result <= multiplier_ready;
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load_result <= multiplier_ready;
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-- ignore multiplier_ready when in automode, the logic will assert auto_done_i when finished
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-- ignore multiplier_ready when in automode, the logic will assert auto_done_i when finished
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done <= ((not run_auto_i) and multiplier_ready) or auto_done_i;
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done <= ((not run_auto_i) and multiplier_ready) or auto_done_i;
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-----------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------
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-- Processes related to op_buffer cntrl and auto_run mode
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-- Processes related to op_buffer cntrl and auto_run mode
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-- start_auto_i -> start autorun mode operation
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-- start_auto_i -> start autorun mode operation
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-- auto_start_pulse <- autorun logic starts the multiplier
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-- auto_start_pulse <- autorun logic starts the multiplier
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-- auto_done <- autorun logic signals when autorun operation has finished
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-- auto_done <- autorun logic signals when autorun operation has finished
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-- x_sel_buffer_i <- autorun logic determines which operand is used as x
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-- x_sel_buffer_i <- autorun logic determines which operand is used as x
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-- check buffer empty signal
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-- check buffer empty signal
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-----------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------
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-- at the beginning of each new multiplication we store the current autorun bit
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-- at the beginning of each new multiplication we store the current autorun bit
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-- STORE_AUTORUN_PROC: process(clk)
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-- STORE_AUTORUN_PROC: process(clk)
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-- begin
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-- begin
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-- if rising_edge(clk) then
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-- if rising_edge(clk) then
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-- if store_autorun_i = '1' then
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-- if store_autorun_i = '1' then
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-- run_auto_stored_i <= run_auto;
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-- run_auto_stored_i <= run_auto;
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-- else
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-- else
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-- run_auto_stored_i <= run_auto_stored_i;
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-- run_auto_stored_i <= run_auto_stored_i;
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-- end if;
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-- end if;
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-- end if;
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-- end if;
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-- end process STORE_AUTORUN_PROC;
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-- end process STORE_AUTORUN_PROC;
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run_auto_i <= run_auto;
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run_auto_i <= run_auto;
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--run_auto_i <= run_auto or run_auto_stored_i;
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-- multiplier_ready is only passed to autorun control when in autorun mode
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-- multiplier_ready is only passed to autorun control when in autorun mode
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auto_multiplier_done_i <= (multiplier_ready and run_auto_i);
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auto_multiplier_done_i <= (multiplier_ready and run_auto_i);
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autorun_control_logic: autorun_cntrl PORT MAP(
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autorun_control_logic : autorun_cntrl port map(
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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start => start_auto_i,
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start => start_auto_i,
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done => auto_done_i,
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done => auto_done_i,
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op_sel => x_sel_buffer_i,
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op_sel => x_sel_buffer_i,
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start_multiplier => auto_start_pulse_i,
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start_multiplier => auto_start_pulse_i,
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multiplier_done => auto_multiplier_done_i,
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multiplier_done => auto_multiplier_done_i,
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read_buffer => read_buffer,
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read_buffer => read_buffer,
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buffer_din => op_sel_buffer,
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buffer_din => op_sel_buffer,
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buffer_empty => op_buffer_empty
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buffer_empty => op_buffer_empty
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);
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);
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end Behavioral;
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end Behavioral;
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No newline at end of file
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No newline at end of file
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