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Line 85... |
ready : out std_logic
|
ready : out std_logic
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);
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);
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end mont_multiplier;
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end mont_multiplier;
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architecture Structural of mont_multiplier is
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architecture Structural of mont_multiplier is
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constant t : integer := nr_stages;
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constant tl : integer := stages_low;
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constant s : integer := n/nr_stages; -- stage width (# bits)
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constant s : integer := n/nr_stages; -- stage width (# bits)
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constant nl : integer := s*tl; -- lower pipeline width (# bits)
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constant nh : integer := n - nl; -- higher pipeline width (# bits)
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|
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signal reset_multiplier : std_logic;
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signal reset_multiplier : std_logic;
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signal start_multiplier : std_logic;
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signal start_multiplier : std_logic;
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|
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signal t_sel : integer range 0 to t; -- width in stages of selected pipeline part
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signal n_sel : integer range 0 to n; -- width in bits of selected pipeline part
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signal next_xi : std_logic;
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signal next_xi : std_logic;
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signal xi : std_logic;
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signal xi : std_logic;
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|
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signal start_first_stage : std_logic;
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signal start_first_stage : std_logic;
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|
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Line 134... |
next_x => next_xi,
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next_x => next_xi,
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p_sel => p_sel,
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p_sel => p_sel,
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xi => xi
|
xi => xi
|
);
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);
|
|
|
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-- this module controls the pipeline operation
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-- width in stages for selected pipeline
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|
with p_sel select
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t_sel <= tl when "01", -- lower pipeline part
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t-tl when "10", -- higher pipeline part
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t when others; -- full pipeline
|
|
|
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-- width in bits for selected pipeline
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with p_sel select
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|
n_sel <= nl-1 when "01", -- lower pipeline part
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nh-1 when "10", -- higher pipeline part
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n-1 when others; -- full pipeline
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|
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-- stepping control logic to keep track off the multiplication and when it is done
|
-- stepping control logic to keep track off the multiplication and when it is done
|
stepping_control : stepping_logic
|
stepping_control : stepping_logic
|
generic map(
|
generic map(
|
n => n, -- max nr of steps required to complete a multiplication
|
n => n, -- max nr of steps required to complete a multiplication
|
t => nr_stages -- total nr of steps in the pipeline
|
t => nr_stages -- total nr of steps in the pipeline
|
)
|
)
|
port map(
|
port map(
|
core_clk => core_clk,
|
core_clk => core_clk,
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start => start_multiplier,
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start => start_multiplier,
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reset => reset_multiplier,
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reset => reset_multiplier,
|
t_sel => nr_stages,
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t_sel => t_sel,
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n_sel => n-1,
|
n_sel => n_sel,
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start_first_stage => start_first_stage,
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start_first_stage => start_first_stage,
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stepping_done => ready
|
stepping_done => ready
|
);
|
);
|
|
|
systolic_array : sys_pipeline
|
systolic_array : sys_pipeline
|