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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [mont_multiplier.vhd] - Diff between revs 32 and 37

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Rev 32 Rev 37
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--    * result is avaiable on the r bus
--    * result is avaiable on the r bus
-- 
-- 
entity mont_multiplier is
entity mont_multiplier is
  generic (
  generic (
    n          : integer := 1536; -- width of the operands
    n          : integer := 1536; -- width of the operands
    nr_stages  : integer := 96; -- total number of stages
    t     : integer := 96;    -- total number of stages (minimum 2)
    stages_low : integer := 32  -- lower number of stages
    tl    : integer := 32;    -- lower number of stages (minimum 1)
 
    split : boolean := true   -- if true the pipeline wil be split in 2 parts,
 
                              -- if false there are no lower stages, only t counts
  );
  );
  port (
  port (
    -- clock input
    -- clock input
    core_clk : in std_logic;
    core_clk : in std_logic;
    -- operand inputs
    -- operand inputs
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    ready    : out std_logic
    ready    : out std_logic
  );
  );
end mont_multiplier;
end mont_multiplier;
 
 
architecture Structural of mont_multiplier is
architecture Structural of mont_multiplier is
  constant t  : integer := nr_stages;
  constant s  : integer := n/t;   -- stage width (# bits)
  constant tl : integer := stages_low;
 
  constant s  : integer := n/nr_stages;   -- stage width (# bits)
 
  constant nl : integer := s*tl;  -- lower pipeline width (# bits)
  constant nl : integer := s*tl;  -- lower pipeline width (# bits)
  constant nh : integer :=  n - nl; -- higher pipeline width (# bits)
  constant nh : integer :=  n - nl; -- higher pipeline width (# bits)
 
 
  signal reset_multiplier : std_logic;
  signal reset_multiplier : std_logic;
  signal start_multiplier : std_logic;
  signal start_multiplier : std_logic;
 
 
 
  signal p_sel_i : std_logic_vector(1 downto 0);
  signal t_sel  : integer range 0 to t;  -- width in stages of selected pipeline part
  signal t_sel  : integer range 0 to t;  -- width in stages of selected pipeline part
  signal n_sel  : integer range 0 to n;  -- width in bits of selected pipeline part
  signal n_sel  : integer range 0 to n;  -- width in bits of selected pipeline part
 
 
  signal next_xi : std_logic;
  signal next_xi : std_logic;
  signal xi : std_logic;
  signal xi : std_logic;
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  -- register to store the x value in 
  -- register to store the x value in 
  -- outputs the operand in serial using a shift register 
  -- outputs the operand in serial using a shift register 
  x_selection : x_shift_reg
  x_selection : x_shift_reg
  generic map(
  generic map(
    n  => n,
    n  => n,
    t  => nr_stages,
    t  => t,
    tl => stages_low
    tl => tl
  )
  )
  port map(
  port map(
    clk    => core_clk,
    clk    => core_clk,
    reset  => reset,
    reset  => reset,
    x_in   => xy,
    x_in   => xy,
    load_x => load_x,
    load_x => load_x,
    next_x => next_xi,
    next_x => next_xi,
    p_sel  => p_sel,
    p_sel  => p_sel_i,
    xi     => xi
    xi     => xi
  );
  );
 
 
 
----------------------------------------
 
-- SINGLE PIPELINE ASSIGNMENTS
 
----------------------------------------
 
single_pipeline : if split=false generate
 
  p_sel_i <= "11";
 
  t_sel <= t;
 
  n_sel <= n-1;
 
end generate;
 
 
 
----------------------------------------
 
-- SPLIT PIPELINE ASSIGNMENTS
 
----------------------------------------
 
split_pipeline : if split=true generate
  -- this module controls the pipeline operation
  -- this module controls the pipeline operation
  --   width in stages for selected pipeline
  --   width in stages for selected pipeline
  with p_sel select
  with p_sel select
    t_sel <=    tl when "01",   -- lower pipeline part
    t_sel <=    tl when "01",   -- lower pipeline part
              t-tl when "10",   -- higher pipeline part
              t-tl when "10",   -- higher pipeline part
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  with p_sel select
  with p_sel select
    n_sel <= nl-1 when "01",  -- lower pipeline part
    n_sel <= nl-1 when "01",  -- lower pipeline part
             nh-1 when "10",  -- higher pipeline part
             nh-1 when "10",  -- higher pipeline part
             n-1 when others; -- full pipeline
             n-1 when others; -- full pipeline
 
 
 
  p_sel_i <= p_sel;
 
end generate;
 
 
  -- stepping control logic to keep track off the multiplication and when it is done
  -- stepping control logic to keep track off the multiplication and when it is done
  stepping_control : stepping_logic
  stepping_control : stepping_logic
  generic map(
  generic map(
    n => n, -- max nr of steps required to complete a multiplication
    n => n, -- max nr of steps required to complete a multiplication
    t => nr_stages -- total nr of steps in the pipeline
    t => t -- total nr of steps in the pipeline
  )
  )
  port map(
  port map(
    core_clk          => core_clk,
    core_clk          => core_clk,
    start             => start_multiplier,
    start             => start_multiplier,
    reset             => reset_multiplier,
    reset             => reset_multiplier,
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  );
  );
 
 
  systolic_array : sys_pipeline
  systolic_array : sys_pipeline
  generic map(
  generic map(
    n  => n,
    n  => n,
    t  => nr_stages,
    t  => t,
    tl => stages_low
    tl => tl,
 
    split => split
  )
  )
  port map(
  port map(
    core_clk => core_clk,
    core_clk => core_clk,
    y       => xy,
    y       => xy,
    m       => m,
    m       => m,
    xi      => xi,
    xi      => xi,
    next_x  => next_xi,
    next_x  => next_xi,
    start   => start_first_stage,
    start   => start_first_stage,
    reset   => reset_multiplier,
    reset   => reset_multiplier,
    p_sel   => p_sel,
    p_sel   => p_sel_i,
    r       => r
    r       => r
  );
  );
 
 
end Structural;
end Structural;
 
 
 
 
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