--------------------------------------------------------------------------------
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----------------------------------------------------------------------
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---- operand_dp ----
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---- ----
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---- This file is part of the ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- ----
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---- Description ----
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---- 4 x 512 bit dual port ram for the operands ----
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---- 32 bit read and write for bus side and 512 bit read and ----
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---- write for multiplier side ----
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---- ----
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---- Dependencies: none ----
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---- ----
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---- Authors: ----
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---- - Geoffrey Ottoy, DraMCo research group ----
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---- - Jonas De Craene, JonasDC@opencores.org ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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-- This file is owned and controlled by Xilinx and must be used --
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-- This file is owned and controlled by Xilinx and must be used --
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-- solely for design, simulation, implementation and creation of --
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-- solely for design, simulation, implementation and creation of --
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-- design files limited to Xilinx devices or technologies. Use --
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-- design files limited to Xilinx devices or technologies. Use --
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-- with non-Xilinx devices or technologies is expressly prohibited --
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-- with non-Xilinx devices or technologies is expressly prohibited --
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-- and immediately terminates your license. --
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-- and immediately terminates your license. --
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-- --
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-- --
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-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
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-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
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-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
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-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
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-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
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-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
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-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
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-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
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-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
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-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
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-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
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-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
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-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
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-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
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-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
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-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
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-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
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-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
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-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
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-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
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-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
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-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
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-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
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-- FOR A PARTICULAR PURPOSE. --
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-- FOR A PARTICULAR PURPOSE. --
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-- --
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-- --
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-- Xilinx products are not intended for use in life support --
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-- Xilinx products are not intended for use in life support --
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-- appliances, devices, or systems. Use in such applications are --
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-- appliances, devices, or systems. Use in such applications are --
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-- expressly prohibited. --
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-- expressly prohibited. --
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-- --
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-- --
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-- (c) Copyright 1995-2009 Xilinx, Inc. --
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-- (c) Copyright 1995-2009 Xilinx, Inc. --
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-- All rights reserved. --
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-- All rights reserved. --
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--------------------------------------------------------------------------------
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----------------------------------------------------------------------
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-- You must compile the wrapper file operand_dp.vhd when simulating
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-- You must compile the wrapper file operand_dp.vhd when simulating
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-- the core, operand_dp. When compiling the wrapper file, be sure to
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-- the core, operand_dp. When compiling the wrapper file, be sure to
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-- reference the XilinxCoreLib VHDL simulation library. For detailed
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-- reference the XilinxCoreLib VHDL simulation library. For detailed
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-- instructions, please refer to the "CORE Generator Help".
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-- instructions, please refer to the "CORE Generator Help".
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-- The synthesis directives "translate_off/translate_on" specified
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-- The synthesis directives "translate_off/translate_on" specified
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-- below are supported by Xilinx, Mentor Graphics and Synplicity
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-- below are supported by Xilinx, Mentor Graphics and Synplicity
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-- synthesis tools. Ensure they are correct for your synthesis tool(s).
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-- synthesis tools. Ensure they are correct for your synthesis tool(s).
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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library ieee;
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use ieee.std_logic_1164.ALL;
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-- synthesis translate_off
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-- synthesis translate_off
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Library XilinxCoreLib;
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library XilinxCoreLib;
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-- synthesis translate_on
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-- synthesis translate_on
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ENTITY operand_dp IS
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entity operand_dp is
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port (
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port (
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clka: IN std_logic;
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clka : in std_logic;
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wea: IN std_logic_VECTOR(0 downto 0);
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wea : in std_logic_vector(0 downto 0);
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addra: IN std_logic_VECTOR(5 downto 0);
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addra : in std_logic_vector(5 downto 0);
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dina: IN std_logic_VECTOR(31 downto 0);
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dina : in std_logic_vector(31 downto 0);
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douta: OUT std_logic_VECTOR(511 downto 0);
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douta : out std_logic_vector(511 downto 0);
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clkb: IN std_logic;
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clkb : in std_logic;
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web: IN std_logic_VECTOR(0 downto 0);
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web : in std_logic_vector(0 downto 0);
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addrb: IN std_logic_VECTOR(5 downto 0);
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addrb : in std_logic_vector(5 downto 0);
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dinb: IN std_logic_VECTOR(511 downto 0);
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dinb : in std_logic_vector(511 downto 0);
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doutb: OUT std_logic_VECTOR(31 downto 0));
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doutb : out std_logic_vector(31 downto 0)
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END operand_dp;
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);
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end operand_dp;
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ARCHITECTURE operand_dp_a OF operand_dp IS
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architecture operand_dp_a of operand_dp is
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-- synthesis translate_off
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-- synthesis translate_off
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component wrapped_operand_dp
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component wrapped_operand_dp
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port (
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port (
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clka: IN std_logic;
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clka : in std_logic;
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wea: IN std_logic_VECTOR(0 downto 0);
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wea : in std_logic_vector(0 downto 0);
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addra: IN std_logic_VECTOR(5 downto 0);
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addra : in std_logic_vector(5 downto 0);
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dina: IN std_logic_VECTOR(31 downto 0);
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dina : in std_logic_vector(31 downto 0);
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douta: OUT std_logic_VECTOR(511 downto 0);
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douta : out std_logic_vector(511 downto 0);
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clkb: IN std_logic;
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clkb : in std_logic;
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web: IN std_logic_VECTOR(0 downto 0);
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web : in std_logic_vector(0 downto 0);
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addrb: IN std_logic_VECTOR(5 downto 0);
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addrb : in std_logic_vector(5 downto 0);
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dinb: IN std_logic_VECTOR(511 downto 0);
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dinb : in std_logic_vector(511 downto 0);
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doutb: OUT std_logic_VECTOR(31 downto 0));
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doutb : out std_logic_vector(31 downto 0)
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);
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end component;
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end component;
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-- Configuration specification
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-- Configuration specification
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for all : wrapped_operand_dp use entity XilinxCoreLib.blk_mem_gen_v3_3(behavioral)
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for all : wrapped_operand_dp use entity XilinxCoreLib.blk_mem_gen_v3_3(behavioral)
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generic map(
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generic map(
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c_has_regceb => 0,
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c_has_regceb => 0,
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c_has_regcea => 0,
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c_has_regcea => 0,
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c_mem_type => 2,
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c_mem_type => 2,
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c_rstram_b => 0,
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c_rstram_b => 0,
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c_rstram_a => 0,
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c_rstram_a => 0,
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c_has_injecterr => 0,
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c_has_injecterr => 0,
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c_rst_type => "SYNC",
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c_rst_type => "SYNC",
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c_prim_type => 1,
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c_prim_type => 1,
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c_read_width_b => 32,
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c_read_width_b => 32,
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c_initb_val => "0",
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c_initb_val => "0",
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c_family => "virtex6",
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c_family => "virtex6",
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c_read_width_a => 512,
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c_read_width_a => 512,
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c_disable_warn_bhv_coll => 0,
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c_disable_warn_bhv_coll => 0,
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c_write_mode_b => "WRITE_FIRST",
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c_write_mode_b => "WRITE_FIRST",
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c_init_file_name => "no_coe_file_loaded",
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c_init_file_name => "no_coe_file_loaded",
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c_write_mode_a => "WRITE_FIRST",
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c_write_mode_a => "WRITE_FIRST",
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c_mux_pipeline_stages => 0,
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c_mux_pipeline_stages => 0,
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c_has_mem_output_regs_b => 0,
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c_has_mem_output_regs_b => 0,
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c_has_mem_output_regs_a => 0,
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c_has_mem_output_regs_a => 0,
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c_load_init_file => 0,
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c_load_init_file => 0,
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c_xdevicefamily => "virtex6",
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c_xdevicefamily => "virtex6",
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c_write_depth_b => 4,
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c_write_depth_b => 4,
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c_write_depth_a => 64,
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c_write_depth_a => 64,
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c_has_rstb => 0,
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c_has_rstb => 0,
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c_has_rsta => 0,
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c_has_rsta => 0,
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c_has_mux_output_regs_b => 0,
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c_has_mux_output_regs_b => 0,
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c_inita_val => "0",
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c_inita_val => "0",
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c_has_mux_output_regs_a => 0,
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c_has_mux_output_regs_a => 0,
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c_addra_width => 6,
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c_addra_width => 6,
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c_addrb_width => 6,
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c_addrb_width => 6,
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c_default_data => "0",
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c_default_data => "0",
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c_use_ecc => 0,
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c_use_ecc => 0,
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c_algorithm => 1,
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c_algorithm => 1,
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c_disable_warn_bhv_range => 0,
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c_disable_warn_bhv_range => 0,
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c_write_width_b => 512,
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c_write_width_b => 512,
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c_write_width_a => 32,
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c_write_width_a => 32,
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c_read_depth_b => 64,
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c_read_depth_b => 64,
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c_read_depth_a => 4,
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c_read_depth_a => 4,
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c_byte_size => 9,
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c_byte_size => 9,
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c_sim_collision_check => "ALL",
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c_sim_collision_check => "ALL",
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c_common_clk => 0,
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c_common_clk => 0,
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c_wea_width => 1,
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c_wea_width => 1,
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c_has_enb => 0,
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c_has_enb => 0,
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c_web_width => 1,
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c_web_width => 1,
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c_has_ena => 0,
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c_has_ena => 0,
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c_use_byte_web => 0,
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c_use_byte_web => 0,
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c_use_byte_wea => 0,
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c_use_byte_wea => 0,
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c_rst_priority_b => "CE",
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c_rst_priority_b => "CE",
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c_rst_priority_a => "CE",
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c_rst_priority_a => "CE",
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c_use_default_data => 0);
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c_use_default_data => 0
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);
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-- synthesis translate_on
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-- synthesis translate_on
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BEGIN
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begin
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-- synthesis translate_off
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-- synthesis translate_off
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U0 : wrapped_operand_dp
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U0 : wrapped_operand_dp
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port map (
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port map (
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clka => clka,
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clka => clka,
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wea => wea,
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wea => wea,
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addra => addra,
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addra => addra,
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dina => dina,
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dina => dina,
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douta => douta,
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douta => douta,
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clkb => clkb,
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clkb => clkb,
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web => web,
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web => web,
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addrb => addrb,
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addrb => addrb,
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dinb => dinb,
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dinb => dinb,
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doutb => doutb);
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doutb => doutb
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);
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-- synthesis translate_on
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-- synthesis translate_on
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END operand_dp_a;
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end operand_dp_a;
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No newline at end of file
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No newline at end of file
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