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library mod_sim_exp;
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library mod_sim_exp;
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use mod_sim_exp.mod_sim_exp_pkg.all;
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use mod_sim_exp.mod_sim_exp_pkg.all;
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use mod_sim_exp.std_functions.all;
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use mod_sim_exp.std_functions.all;
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-- address structure:
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-- address structure:
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-- bit: highest -> '1': modulus
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-- bit: 8 -> '1': modulus
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-- '0': operands
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-- '0': operands
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-- bits: (highest-1)-log2(width/32) -> operand_in_sel in case of highest bit = '0'
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-- bits: 7-6 -> operand_in_sel in case of highest bit = '0'
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-- modulus_in_sel in case of highest bit = '1'
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-- modulus_in_sel in case of highest bit = '1'
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-- bits: (log2(width/32)-1)-0 -> modulus_addr / operand_addr resp.
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-- bits: (log2(width/32)-1)-0 -> modulus_addr / operand_addr resp.
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--
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--
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entity operand_mem is
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entity operand_mem is
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generic(
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generic(
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-- system clock
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-- system clock
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clk : in std_logic;
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clk : in std_logic;
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-- data interface (plb side)
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-- data interface (plb side)
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data_in : in std_logic_vector(31 downto 0);
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data_in : in std_logic_vector(31 downto 0);
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data_out : out std_logic_vector(31 downto 0);
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data_out : out std_logic_vector(31 downto 0);
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rw_address : in std_logic_vector(log2(nr_op)+log2(width/32) downto 0);
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rw_address : in std_logic_vector(8 downto 0);
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write_enable : in std_logic;
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write_enable : in std_logic;
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-- operand interface (multiplier side)
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-- operand interface (multiplier side)
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op_sel : in std_logic_vector(log2(nr_op)-1 downto 0);
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op_sel : in std_logic_vector(log2(nr_op)-1 downto 0);
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xy_out : out std_logic_vector((width-1) downto 0);
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xy_out : out std_logic_vector((width-1) downto 0);
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m : out std_logic_vector((width-1) downto 0);
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m : out std_logic_vector((width-1) downto 0);
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begin
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begin
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-- map inputs
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-- map inputs
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xy_addr_i <= rw_address(wordaddr_aw-1 downto 0);
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xy_addr_i <= rw_address(wordaddr_aw-1 downto 0);
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m_addr_i <= rw_address(wordaddr_aw-1 downto 0);
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m_addr_i <= rw_address(wordaddr_aw-1 downto 0);
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operand_in_sel_i <= rw_address(total_aw-2 downto wordaddr_aw);
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operand_in_sel_i <= rw_address(7 downto 6);
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modulus_in_sel_i <= rw_address(wordaddr_aw+maddr_aw-1 downto wordaddr_aw);
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modulus_in_sel_i <= rw_address(6 downto 6);
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xy_data_i <= data_in;
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xy_data_i <= data_in;
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m_data_i <= data_in;
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m_data_i <= data_in;
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-- select right memory with highest address bit
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-- select right memory with highest address bit
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load_op <= write_enable when (rw_address(total_aw-1) = '0') else '0';
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load_op <= write_enable when (rw_address(8) = '0') else '0';
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load_m <= write_enable when (rw_address(total_aw-1) = '1') else '0';
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load_m <= write_enable when (rw_address(8) = '1') else '0';
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xil_prim_RAM : if mem_style="xil_prim" generate
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xil_prim_RAM : if mem_style="xil_prim" generate
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-- xy operand storage
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-- xy operand storage
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xy_ram_xil : operand_ram
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xy_ram_xil : operand_ram
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port map(
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port map(
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