| Line 70... |
Line 70... |
generic(
|
generic(
|
width : integer := 1536; -- width of the operands
|
width : integer := 1536; -- width of the operands
|
nr_op : integer := 4; -- nr of operand storages, has to be greater than nr_m
|
nr_op : integer := 4; -- nr of operand storages, has to be greater than nr_m
|
nr_m : integer := 2; -- nr of modulus storages
|
nr_m : integer := 2; -- nr of modulus storages
|
mem_style : string := "asym"; -- xil_prim, generic, asym are valid options
|
mem_style : string := "asym"; -- xil_prim, generic, asym are valid options
|
device : string := "altera" -- xilinx, altera are valid options
|
device : string := "xilinx" -- xilinx, altera are valid options
|
);
|
);
|
port(
|
port(
|
-- system clock
|
|
clk : in std_logic;
|
|
-- data interface (plb side)
|
-- data interface (plb side)
|
|
bus_clk : in std_logic;
|
data_in : in std_logic_vector(31 downto 0);
|
data_in : in std_logic_vector(31 downto 0);
|
data_out : out std_logic_vector(31 downto 0);
|
data_out : out std_logic_vector(31 downto 0);
|
rw_address : in std_logic_vector(8 downto 0);
|
rw_address : in std_logic_vector(8 downto 0);
|
write_enable : in std_logic;
|
write_enable : in std_logic;
|
-- operand interface (multiplier side)
|
-- operand interface (multiplier side)
|
|
core_clk : in std_logic;
|
op_sel : in std_logic_vector(log2(nr_op)-1 downto 0);
|
op_sel : in std_logic_vector(log2(nr_op)-1 downto 0);
|
xy_out : out std_logic_vector((width-1) downto 0);
|
xy_out : out std_logic_vector((width-1) downto 0);
|
m : out std_logic_vector((width-1) downto 0);
|
m : out std_logic_vector((width-1) downto 0);
|
result_in : in std_logic_vector((width-1) downto 0);
|
result_in : in std_logic_vector((width-1) downto 0);
|
-- control signals
|
-- control signals
|
| Line 130... |
Line 130... |
|
|
xil_prim_RAM : if mem_style="xil_prim" generate
|
xil_prim_RAM : if mem_style="xil_prim" generate
|
-- xy operand storage
|
-- xy operand storage
|
xy_ram_xil : operand_ram
|
xy_ram_xil : operand_ram
|
port map(
|
port map(
|
clk => clk,
|
bus_clk => bus_clk,
|
|
core_clk => core_clk,
|
collision => collision,
|
collision => collision,
|
operand_addr => xy_addr_i,
|
operand_addr => xy_addr_i,
|
operand_in => xy_data_i,
|
operand_in => xy_data_i,
|
operand_in_sel => operand_in_sel_i,
|
operand_in_sel => operand_in_sel_i,
|
result_out => data_out,
|
result_out => data_out,
|
| Line 147... |
Line 148... |
);
|
);
|
|
|
-- modulus storage
|
-- modulus storage
|
m_ram_xil : modulus_ram
|
m_ram_xil : modulus_ram
|
port map(
|
port map(
|
clk => clk,
|
clk => bus_clk,
|
modulus_addr => m_addr_i,
|
modulus_addr => m_addr_i,
|
write_modulus => load_m,
|
write_modulus => load_m,
|
modulus_in => m_data_i,
|
modulus_in => m_data_i,
|
modulus_out => m
|
modulus_out => m
|
);
|
);
|
| Line 163... |
Line 164... |
generic map(
|
generic map(
|
width => width,
|
width => width,
|
depth => nr_op
|
depth => nr_op
|
)
|
)
|
port map(
|
port map(
|
clk => clk,
|
|
collision => collision,
|
collision => collision,
|
|
bus_clk => bus_clk,
|
operand_addr => xy_addr_i,
|
operand_addr => xy_addr_i,
|
operand_in => xy_data_i,
|
operand_in => xy_data_i,
|
operand_in_sel => operand_in_sel_i,
|
operand_in_sel => operand_in_sel_i,
|
result_out => data_out,
|
result_out => data_out,
|
write_operand => load_op,
|
write_operand => load_op,
|
operand_out => xy_out,
|
operand_out => xy_out,
|
operand_out_sel => op_sel,
|
operand_out_sel => op_sel,
|
result_dest_op => result_dest_op,
|
result_dest_op => result_dest_op,
|
|
core_clk => core_clk,
|
write_result => load_result,
|
write_result => load_result,
|
result_in => result_in
|
result_in => result_in
|
);
|
);
|
|
|
-- modulus storage
|
-- modulus storage
|
| Line 184... |
Line 186... |
generic map(
|
generic map(
|
width => width,
|
width => width,
|
depth => nr_m
|
depth => nr_m
|
)
|
)
|
port map(
|
port map(
|
clk => clk,
|
bus_clk => bus_clk,
|
modulus_in_sel => modulus_in_sel_i,
|
modulus_in_sel => modulus_in_sel_i,
|
modulus_addr => m_addr_i,
|
modulus_addr => m_addr_i,
|
write_modulus => load_m,
|
write_modulus => load_m,
|
modulus_in => m_data_i,
|
modulus_in => m_data_i,
|
|
core_clk => core_clk,
|
modulus_out => m,
|
modulus_out => m,
|
modulus_sel => modulus_sel
|
modulus_sel => modulus_sel
|
);
|
);
|
end generate;
|
end generate;
|
|
|
| Line 203... |
Line 206... |
width => width,
|
width => width,
|
depth => nr_op,
|
depth => nr_op,
|
device => device
|
device => device
|
)
|
)
|
port map(
|
port map(
|
clk => clk,
|
|
collision => collision,
|
collision => collision,
|
|
bus_clk => bus_clk,
|
operand_addr => xy_addr_i,
|
operand_addr => xy_addr_i,
|
operand_in => xy_data_i,
|
operand_in => xy_data_i,
|
operand_in_sel => operand_in_sel_i,
|
operand_in_sel => operand_in_sel_i,
|
result_out => data_out,
|
result_out => data_out,
|
write_operand => load_op,
|
write_operand => load_op,
|
operand_out => xy_out,
|
operand_out => xy_out,
|
operand_out_sel => op_sel,
|
operand_out_sel => op_sel,
|
result_dest_op => result_dest_op,
|
result_dest_op => result_dest_op,
|
|
core_clk => core_clk,
|
write_result => load_result,
|
write_result => load_result,
|
result_in => result_in
|
result_in => result_in
|
);
|
);
|
|
|
-- modulus storage
|
-- modulus storage
|
| Line 225... |
Line 229... |
width => width,
|
width => width,
|
depth => nr_m,
|
depth => nr_m,
|
device => device
|
device => device
|
)
|
)
|
port map(
|
port map(
|
clk => clk,
|
bus_clk => bus_clk,
|
modulus_in_sel => modulus_in_sel_i,
|
modulus_in_sel => modulus_in_sel_i,
|
modulus_addr => m_addr_i,
|
modulus_addr => m_addr_i,
|
write_modulus => load_m,
|
write_modulus => load_m,
|
modulus_in => m_data_i,
|
modulus_in => m_data_i,
|
|
core_clk => core_clk,
|
modulus_out => m,
|
modulus_out => m,
|
modulus_sel => modulus_sel
|
modulus_sel => modulus_sel
|
);
|
);
|
end generate;
|
end generate;
|
|
|
