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------------------------------------------------------------------------------------
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----------------------------------------------------------------------
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--
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---- operand_ram ----
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-- Geoffrey Ottoy - DraMCo research group
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---- ----
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--
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---- This file is part of the ----
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-- Module Name: operand_mem.vhd / entity operand_mem
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---- Modular Simultaneous Exponentiation Core project ----
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--
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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-- Last Modified: 25/04/2012
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---- ----
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--
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---- Description ----
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-- Description: BRAM memory and logic to the store 4 (1536-bit) operands and the
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---- BRAM memory and logic to the store 4 (1536-bit) operands ----
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-- modulus for the montgomery multiplier
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---- for the montgomery multiplier ----
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--
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---- ----
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--
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---- Dependencies: ----
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-- Dependencies: operand_dp (coregen)
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---- - operand_dp (coregen) ----
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--
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---- ----
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-- Revision:
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---- Authors: ----
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-- Revision 1.01 - added "result_dest_op" input
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---- - Geoffrey Ottoy, DraMCo research group ----
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-- Revision 1.00 - Architecture
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---- - Jonas De Craene, JonasDC@opencores.org ----
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-- Revision 0.01 - File Created
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---- ----
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-- Additional Comments:
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----------------------------------------------------------------------
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--
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---- ----
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--
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
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------------------------------------------------------------------------------------
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---- ----
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--
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---- This source file may be used and distributed without ----
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-- NOTICE:
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---- restriction provided that this copyright statement is not ----
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--
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---- removed from the file and that any derivative work contains ----
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-- Copyright DraMCo research group. 2011. This code may be contain portions patented
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---- the original copyright notice and the associated disclaimer. ----
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-- by other third parties!
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---- ----
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--
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---- This source file is free software; you can redistribute it ----
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------------------------------------------------------------------------------------
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---- and/or modify it under the terms of the GNU Lesser General ----
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library IEEE;
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---- Public License as published by the Free Software Foundation; ----
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use IEEE.STD_LOGIC_1164.ALL;
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---- either version 2.1 of the License, or (at your option) any ----
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use IEEE.STD_LOGIC_ARITH.ALL;
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---- later version. ----
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- Uncomment the following library declaration if instantiating
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- any Xilinx primitives in this code.
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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--library UNISIM;
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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--use UNISIM.VComponents.all;
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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library mod_sim_exp;
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use mod_sim_exp.mod_sim_exp_pkg.all;
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entity operand_ram is
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entity operand_ram is
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port( -- write_operand_ack voorzien?
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port( -- write_operand_ack voorzien?
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-- global ports
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-- global ports
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clk : in std_logic;
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clk : in std_logic;
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operand_addr : in std_logic_vector(5 downto 0);
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operand_addr : in std_logic_vector(5 downto 0);
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operand_in : in std_logic_vector(31 downto 0);
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operand_in : in std_logic_vector(31 downto 0);
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operand_in_sel : in std_logic_vector(1 downto 0);
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operand_in_sel : in std_logic_vector(1 downto 0);
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result_out : out std_logic_vector(31 downto 0);
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result_out : out std_logic_vector(31 downto 0);
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write_operand : in std_logic;
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write_operand : in std_logic;
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-- multiplier side connections (+1024 bit parallel)
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-- multiplier side connections (1536 bit parallel)
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result_dest_op : in std_logic_vector(1 downto 0);
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result_dest_op : in std_logic_vector(1 downto 0);
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operand_out : out std_logic_vector(1535 downto 0);
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operand_out : out std_logic_vector(1535 downto 0);
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operand_out_sel : in std_logic_vector(1 downto 0); -- controlled by bus side :)
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operand_out_sel : in std_logic_vector(1 downto 0); -- controlled by bus side
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write_result : in std_logic;
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write_result : in std_logic;
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result_in : in std_logic_vector(1535 downto 0)
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result_in : in std_logic_vector(1535 downto 0)
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);
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);
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end operand_ram;
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end operand_ram;
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architecture Behavioral of operand_ram is
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-- dual port blockram to store and update operands
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component operand_dp
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port (
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clka: in std_logic;
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wea: in std_logic_vector(0 downto 0);
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addra: in std_logic_vector(5 downto 0);
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dina: in std_logic_vector(31 downto 0);
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douta: out std_logic_vector(511 downto 0);
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clkb: in std_logic;
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web: IN std_logic_VECTOR(0 downto 0);
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addrb: IN std_logic_VECTOR(5 downto 0);
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dinb: IN std_logic_VECTOR(511 downto 0);
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doutb: OUT std_logic_VECTOR(31 downto 0));
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end component;
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architecture Behavioral of operand_ram is
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-- port a signals
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-- port a signals
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signal addra : std_logic_vector(5 downto 0);
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signal addra : std_logic_vector(5 downto 0);
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signal part_enable : std_logic_vector(3 downto 0);
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signal part_enable : std_logic_vector(3 downto 0);
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signal wea : std_logic_vector(3 downto 0);
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signal wea : std_logic_vector(3 downto 0);
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signal write_operand_i : std_logic;
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signal write_operand_i : std_logic;
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signal doutb1 : std_logic_vector(31 downto 0);
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signal doutb1 : std_logic_vector(31 downto 0);
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signal doutb2 : std_logic_vector(31 downto 0);
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signal doutb2 : std_logic_vector(31 downto 0);
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signal doutb3 : std_logic_vector(31 downto 0);
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signal doutb3 : std_logic_vector(31 downto 0);
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begin
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begin
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-- WARNING: Very Important!
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-- WARNING: Very Important!
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-- wea & web signals must never be high at the same time !!
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-- wea & web signals must never be high at the same time !!
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-- web has priority
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-- web has priority
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write_operand_i <= write_operand and not write_result;
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write_operand_i <= write_operand and not write_result;
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web(0) <= write_result;
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web(0) <= write_result;
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"0000" when others;
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"0000" when others;
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-- we can only read back from the result (stored in result_dest_op)
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-- we can only read back from the result (stored in result_dest_op)
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addrb <= result_dest_op & operand_addr(3 downto 0);
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addrb <= result_dest_op & operand_addr(3 downto 0);
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-- register_output_proc: process(clk)
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-- begin
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-- if rising_edge(clk) then
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-- case operand_addr(5 downto 4) is
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-- when "00" =>
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-- result_out <= doutb0;
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-- when "01" =>
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-- result_out <= doutb1;
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-- when "10" =>
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-- result_out <= doutb2;
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-- when others =>
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-- result_out <= doutb3;
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-- end case;
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-- end if;
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-- end process;
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with operand_addr(5 downto 4) select
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with operand_addr(5 downto 4) select
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result_out <= doutb0 when "00",
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result_out <= doutb0 when "00",
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doutb1 when "01",
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doutb1 when "01",
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doutb2 when "10",
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doutb2 when "10",
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doutb3 when others;
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doutb3 when others;
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-- 4 instances of a dual port ram to store the parts of the operand
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-- 3 instances of a dual port ram to store the parts of the operand
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op_0 : operand_dp
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op_0 : operand_dp
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port map (
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port map (
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clka => clk,
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clka => clk,
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wea => wea(0 downto 0),
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wea => wea(0 downto 0),
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addra => addra,
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addra => addra,
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addrb => addrb,
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addrb => addrb,
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dinb => result_in(1535 downto 1024),
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dinb => result_in(1535 downto 1024),
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doutb => doutb2
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doutb => doutb2
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);
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);
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-- op_3 : operand_dp
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-- port map (
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-- clka => clk,
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-- wea => wea(3 downto 3),
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-- addra => addra,
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-- dina => operand_in,
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-- douta => operand_out(2047 downto 1536),
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-- clkb => clk,
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-- web => web,
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-- addrb => addrb,
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-- dinb => result_in(2047 downto 1536),
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-- doutb => doutb3
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-- );
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end Behavioral;
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end Behavioral;
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No newline at end of file
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