----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- operand_ram ----
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---- operand_ram ----
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---- ----
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---- ----
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---- This file is part of the ----
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---- This file is part of the ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- ----
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---- ----
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---- Description ----
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---- Description ----
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---- BRAM memory and logic to the store 4 (1536-bit) operands ----
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---- BRAM memory and logic to the store 4 (1536-bit) operands ----
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---- for the montgomery multiplier ----
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---- for the montgomery multiplier ----
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---- ----
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---- ----
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---- Dependencies: ----
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---- Dependencies: ----
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---- - operand_dp (coregen) ----
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---- - operand_dp (coregen) ----
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---- ----
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---- ----
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---- Authors: ----
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---- Authors: ----
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---- - Geoffrey Ottoy, DraMCo research group ----
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---- - Geoffrey Ottoy, DraMCo research group ----
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---- - Jonas De Craene, JonasDC@opencores.org ----
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---- - Jonas De Craene, JonasDC@opencores.org ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- ----
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---- ----
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
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---- ----
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---- ----
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---- This source file may be used and distributed without ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- later version. ----
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---- ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- details. ----
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---- ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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|
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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|
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library mod_sim_exp;
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library mod_sim_exp;
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use mod_sim_exp.mod_sim_exp_pkg.all;
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use mod_sim_exp.mod_sim_exp_pkg.all;
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entity operand_ram is
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entity operand_ram is
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port( -- write_operand_ack voorzien?
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port( -- write_operand_ack voorzien?
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-- global ports
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-- global ports
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clk : in std_logic;
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collision : out std_logic;
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collision : out std_logic;
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-- bus side connections (32-bit serial)
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-- bus side connections (32-bit serial)
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bus_clk : in std_logic;
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operand_addr : in std_logic_vector(5 downto 0);
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operand_addr : in std_logic_vector(5 downto 0);
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operand_in : in std_logic_vector(31 downto 0);
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operand_in : in std_logic_vector(31 downto 0);
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operand_in_sel : in std_logic_vector(1 downto 0);
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operand_in_sel : in std_logic_vector(1 downto 0);
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result_out : out std_logic_vector(31 downto 0);
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result_out : out std_logic_vector(31 downto 0);
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write_operand : in std_logic;
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write_operand : in std_logic;
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-- multiplier side connections (1536 bit parallel)
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-- multiplier side connections (1536 bit parallel)
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core_clk : in std_logic;
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result_dest_op : in std_logic_vector(1 downto 0);
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result_dest_op : in std_logic_vector(1 downto 0);
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operand_out : out std_logic_vector(1535 downto 0);
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operand_out : out std_logic_vector(1535 downto 0);
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operand_out_sel : in std_logic_vector(1 downto 0); -- controlled by bus side
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operand_out_sel : in std_logic_vector(1 downto 0); -- controlled by bus side
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write_result : in std_logic;
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write_result : in std_logic;
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result_in : in std_logic_vector(1535 downto 0)
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result_in : in std_logic_vector(1535 downto 0)
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);
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);
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end operand_ram;
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end operand_ram;
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architecture Behavioral of operand_ram is
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architecture Behavioral of operand_ram is
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-- port a signals
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-- port a signals
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signal addra : std_logic_vector(5 downto 0);
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signal addra : std_logic_vector(5 downto 0);
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signal part_enable : std_logic_vector(3 downto 0);
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signal part_enable : std_logic_vector(3 downto 0);
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signal wea : std_logic_vector(3 downto 0);
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signal wea : std_logic_vector(3 downto 0);
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signal write_operand_i : std_logic;
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signal write_operand_i : std_logic;
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-- port b signals
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-- port b signals
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signal addrb : std_logic_vector(5 downto 0);
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signal addrb : std_logic_vector(1 downto 0);
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signal web : std_logic_vector(0 downto 0);
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signal web : std_logic_vector(0 downto 0);
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signal doutb0 : std_logic_vector(31 downto 0);
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signal douta0 : std_logic_vector(31 downto 0);
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signal doutb1 : std_logic_vector(31 downto 0);
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signal douta1 : std_logic_vector(31 downto 0);
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signal doutb2 : std_logic_vector(31 downto 0);
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signal douta2 : std_logic_vector(31 downto 0);
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begin
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begin
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-- WARNING: Very Important!
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-- WARNING: Very Important!
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-- wea & web signals must never be high at the same time !!
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-- wea & web signals must never be high at the same time !!
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-- web has priority
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-- web has priority
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write_operand_i <= write_operand and not write_result;
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write_operand_i <= write_operand and not write_result;
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web(0) <= write_result;
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web(0) <= write_result;
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collision <= write_operand and write_result;
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collision <= write_operand and write_result;
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-- the dual port ram has a depth of 4 (each layer contains an operand)
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-- the dual port ram has a depth of 4 (each layer contains an operand)
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-- result is always stored in position 3
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-- result is always stored in position 3
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-- doutb is always result
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-- doutb is always result
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with write_operand_i select
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with write_result select
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addra <= operand_in_sel & operand_addr(3 downto 0) when '1',
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addrb <= result_dest_op when '1',
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operand_out_sel & "0000" when others;
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operand_out_sel when others;
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with operand_addr(5 downto 4) select
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with operand_addr(5 downto 4) select
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part_enable <= "0001" when "00",
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part_enable <= "0001" when "00",
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"0010" when "01",
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"0010" when "01",
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"0100" when "10",
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"0100" when "10",
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"1000" when others;
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"1000" when others;
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with write_operand_i select
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with write_operand select
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wea <= part_enable when '1',
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wea <= part_enable when '1',
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"0000" when others;
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"0000" when others;
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-- we can only read back from the result (stored in result_dest_op)
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addra <= operand_in_sel & operand_addr(3 downto 0);
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addrb <= result_dest_op & operand_addr(3 downto 0);
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with operand_addr(5 downto 4) select
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with operand_addr(5 downto 4) select
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result_out <= doutb0 when "00",
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result_out <= douta0 when "00",
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doutb1 when "01",
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douta1 when "01",
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doutb2 when others;
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douta2 when others;
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-- 3 instances of a dual port ram to store the parts of the operand
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-- 3 instances of a dual port ram to store the parts of the operand
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op_0 : operand_dp
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op_0 : operand_dp
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port map (
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port map (
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clka => clk,
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clka => bus_clk,
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wea => wea(0 downto 0),
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wea => wea(0 downto 0),
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addra => addra,
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addra => addra,
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dina => operand_in,
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dina => operand_in,
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douta => operand_out(511 downto 0),
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douta => douta0,
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clkb => clk,
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clkb => core_clk,
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web => web,
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web => web,
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addrb => addrb,
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addrb => addrb,
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dinb => result_in(511 downto 0),
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dinb => result_in(511 downto 0),
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doutb => doutb0
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doutb => operand_out(511 downto 0)
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);
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);
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op_1 : operand_dp
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op_1 : operand_dp
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port map (
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port map (
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clka => clk,
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clka => bus_clk,
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wea => wea(1 downto 1),
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wea => wea(1 downto 1),
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addra => addra,
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addra => addra,
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dina => operand_in,
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dina => operand_in,
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douta => operand_out(1023 downto 512),
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douta => douta1,
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clkb => clk,
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clkb => core_clk,
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web => web,
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web => web,
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addrb => addrb,
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addrb => addrb,
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dinb => result_in(1023 downto 512),
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dinb => result_in(1023 downto 512),
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doutb => doutb1
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doutb => operand_out(1023 downto 512)
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);
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);
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op_2 : operand_dp
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op_2 : operand_dp
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port map (
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port map (
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clka => clk,
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clka => bus_clk,
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wea => wea(2 downto 2),
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wea => wea(2 downto 2),
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addra => addra,
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addra => addra,
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dina => operand_in,
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dina => operand_in,
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douta => operand_out(1535 downto 1024),
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douta => douta2,
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clkb => clk,
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clkb => core_clk,
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web => web,
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web => web,
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addrb => addrb,
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addrb => addrb,
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dinb => result_in(1535 downto 1024),
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dinb => result_in(1535 downto 1024),
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doutb => doutb2
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doutb => operand_out(1535 downto 1024)
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);
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);
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end Behavioral;
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end Behavioral;
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