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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [operand_ram_asym.vhd] - Diff between revs 67 and 69
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Rev 67 |
Rev 69 |
Line 169... |
Line 169... |
weB => write_result,
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weB => write_result,
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dinB => result_in((i+1)*RAMblock_maxwidth-1 downto i*RAMblock_maxwidth),
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dinB => result_in((i+1)*RAMblock_maxwidth-1 downto i*RAMblock_maxwidth),
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doutB => operand_out((i+1)*RAMblock_maxwidth-1 downto i*RAMblock_maxwidth)
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doutB => operand_out((i+1)*RAMblock_maxwidth-1 downto i*RAMblock_maxwidth)
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);
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);
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-- weA, weB
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-- weA, weB
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process (write_operand_i, write_result, operand_addr)
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process (write_operand_i, operand_addr)
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begin
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begin
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if operand_addr(log2(width/32)-1 downto log2(RAMblock_maxwidth/32)) = conv_std_logic_vector(i,RAMselect_aw) then
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if operand_addr(log2(width/32)-1 downto log2(RAMblock_maxwidth/32)) = conv_std_logic_vector(i,RAMselect_aw) then
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weA_RAM(i) <= write_operand_i;
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weA_RAM(i) <= write_operand_i;
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else
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else
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weA_RAM(i) <= '0';
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weA_RAM(i) <= '0';
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Line 218... |
Line 218... |
weB => write_result,
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weB => write_result,
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dinB => result_in(width-1 downto i*RAMblock_maxwidth),
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dinB => result_in(width-1 downto i*RAMblock_maxwidth),
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doutB => operand_out(width-1 downto i*RAMblock_maxwidth)
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doutB => operand_out(width-1 downto i*RAMblock_maxwidth)
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);
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);
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-- weA, weB part
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-- weA, weB part
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process (write_operand_i, write_result, operand_addr)
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process (write_operand_i, operand_addr)
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begin
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begin
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if operand_addr(log2(width/32)-1 downto log2(RAMblock_maxwidth/32)) = conv_std_logic_vector(i,RAMselect_aw) then
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if operand_addr(log2(width/32)-1 downto log2(RAMblock_maxwidth/32)) = conv_std_logic_vector(i,RAMselect_aw) then
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weA_part <= write_operand_i;
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weA_part <= write_operand_i;
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else
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else
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weA_part <= '0';
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weA_part <= '0';
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