----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- operand_ram_asym ----
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---- operand_ram_asym ----
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---- ----
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---- ----
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---- This file is part of the ----
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---- This file is part of the ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- ----
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---- ----
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---- Description ----
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---- Description ----
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---- BRAM memory and logic to store the operands, due to the ----
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---- BRAM memory and logic to store the operands, due to the ----
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---- achitecture, a minimum depth of 2 is needed for this ----
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---- achitecture, a minimum depth of 2 is needed for this ----
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---- module to be inferred into blockram, this version is ----
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---- module to be inferred into blockram, this version is ----
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---- slightly more performant than operand_ram_gen and uses ----
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---- slightly more performant than operand_ram_gen and uses ----
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---- less resources. but does not work on every fpga, only ----
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---- less resources. but does not work on every fpga, only ----
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---- the ones that support asymmetric rams. ----
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---- the ones that support asymmetric rams. ----
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---- ----
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---- ----
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---- Dependencies: ----
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---- Dependencies: ----
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---- - tdpramblock_asym ----
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---- - tdpramblock_asym ----
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---- ----
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---- ----
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---- Authors: ----
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---- Authors: ----
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---- - Geoffrey Ottoy, DraMCo research group ----
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---- - Geoffrey Ottoy, DraMCo research group ----
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---- - Jonas De Craene, JonasDC@opencores.org ----
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---- - Jonas De Craene, JonasDC@opencores.org ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- ----
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---- ----
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
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---- ----
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---- ----
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---- This source file may be used and distributed without ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- later version. ----
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---- ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- details. ----
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---- ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
|
---- You should have received a copy of the GNU Lesser General ----
|
---- Public License along with this source; if not, download it ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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|
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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|
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library mod_sim_exp;
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library mod_sim_exp;
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|
use mod_sim_exp.mod_sim_exp_pkg.all;
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use mod_sim_exp.std_functions.all;
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use mod_sim_exp.std_functions.all;
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|
|
-- structural description of a RAM to hold the operands, with
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-- structural description of a RAM to hold the operands, with
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-- adjustable width (64, 128, 256, 512, 576, 640,..) and depth(nr of operands)
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-- adjustable width (64, 128, 256, 512, 576, 640,..) and depth(nr of operands)
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-- formula for available widths: (i*512+(0 or 64 or 128 or 256)) (i=integer number)
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-- formula for available widths: (i*512+(0 or 64 or 128 or 256)) (i=integer number)
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--
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--
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entity operand_ram_asym is
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entity operand_ram_asym is
|
generic(
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generic(
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width : integer := 1536; -- width of the operands
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width : integer := 1536; -- width of the operands
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depth : integer := 4; -- nr of operands
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depth : integer := 4; -- nr of operands
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device : string := "xilinx"
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device : string := "xilinx"
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);
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);
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port(
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port(
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-- global ports
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-- global ports
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clk : in std_logic;
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clk : in std_logic;
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collision : out std_logic; -- 1 if simultaneous write on RAM
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collision : out std_logic; -- 1 if simultaneous write on RAM
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-- bus side connections (32-bit serial)
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-- bus side connections (32-bit serial)
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write_operand : in std_logic; -- write_enable
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write_operand : in std_logic; -- write_enable
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operand_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to write to
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operand_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to write to
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operand_addr : in std_logic_vector(log2(width/32)-1 downto 0); -- address of operand word to write
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operand_addr : in std_logic_vector(log2(width/32)-1 downto 0); -- address of operand word to write
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operand_in : in std_logic_vector(31 downto 0); -- operand word(32-bit) to write
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operand_in : in std_logic_vector(31 downto 0); -- operand word(32-bit) to write
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result_out : out std_logic_vector(31 downto 0); -- operand out, reading is always result operand
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result_out : out std_logic_vector(31 downto 0); -- operand out, reading is always result operand
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operand_out_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to give to multiplier
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operand_out_sel : in std_logic_vector(log2(depth)-1 downto 0); -- operand to give to multiplier
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-- multiplier side connections (width-bit parallel)
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-- multiplier side connections (width-bit parallel)
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result_dest_op : in std_logic_vector(log2(depth)-1 downto 0); -- operand select for result
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result_dest_op : in std_logic_vector(log2(depth)-1 downto 0); -- operand select for result
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operand_out : out std_logic_vector(width-1 downto 0); -- operand out to multiplier
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operand_out : out std_logic_vector(width-1 downto 0); -- operand out to multiplier
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write_result : in std_logic; -- write enable for multiplier side
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write_result : in std_logic; -- write enable for multiplier side
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result_in : in std_logic_vector(width-1 downto 0) -- result to write from multiplier
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result_in : in std_logic_vector(width-1 downto 0) -- result to write from multiplier
|
);
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);
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end operand_ram_asym;
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end operand_ram_asym;
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|
|
architecture Behavioral of operand_ram_asym is
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architecture Behavioral of operand_ram_asym is
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-- contstants
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-- contstants
|
constant RAMblock_maxwidth : integer := 512;
|
constant RAMblock_maxwidth : integer := 512;
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constant nrRAMblocks_full : integer := width/RAMblock_maxwidth;
|
constant nrRAMblocks_full : integer := width/RAMblock_maxwidth;
|
constant RAMblock_part : integer := width rem RAMblock_maxwidth;
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constant RAMblock_part : integer := width rem RAMblock_maxwidth;
|
constant RAMblock_part_width : integer := width-(nrRAMblocks_full*RAMblock_maxwidth);
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constant RAMblock_part_width : integer := width-(nrRAMblocks_full*RAMblock_maxwidth);
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constant RAMselect_aw : integer := log2(width/32)-log2(nrRAMblocks_full/32);
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constant RAMselect_aw : integer := log2(width/32)-log2(nrRAMblocks_full/32);
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|
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-- internal signals
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-- internal signals
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signal mult_op_sel : std_logic_vector(log2(depth)-1 downto 0);
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signal mult_op_sel : std_logic_vector(log2(depth)-1 downto 0);
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signal write_operand_i : std_logic;
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signal write_operand_i : std_logic;
|
begin
|
begin
|
-- WARNING: Very Important!
|
-- WARNING: Very Important!
|
-- wea & web signals must never be high at the same time !!
|
-- wea & web signals must never be high at the same time !!
|
-- web has priority
|
-- web has priority
|
write_operand_i <= write_operand and not write_result; -- portB has write priority
|
write_operand_i <= write_operand and not write_result; -- portB has write priority
|
collision <= write_operand and write_result;
|
collision <= write_operand and write_result;
|
|
|
-- when multiplier is writing back result, select the result address
|
-- when multiplier is writing back result, select the result address
|
with write_result select
|
with write_result select
|
mult_op_sel <= result_dest_op when '1',
|
mult_op_sel <= result_dest_op when '1',
|
operand_out_sel when others;
|
operand_out_sel when others;
|
|
|
-- generate (width/512) ramblocks with a given depth
|
-- generate (width/512) ramblocks with a given depth
|
-- these rams are tyed together to form the following structure
|
-- these rams are tyed together to form the following structure
|
-- True dual port ram:
|
-- True dual port ram:
|
-- - PORT A : 32-bit write | 32-bit read
|
-- - PORT A : 32-bit write | 32-bit read
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-- - PORT B : (width)-bit write | (width)-bit read
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-- - PORT B : (width)-bit write | (width)-bit read
|
--
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--
|
single_block : if (width <= RAMblock_maxwidth) generate
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single_block : if (width <= RAMblock_maxwidth) generate
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-- signals for single block
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-- signals for single block
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signal addrA_single : std_logic_vector(log2(width*depth/32)-1 downto 0);
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signal addrA_single : std_logic_vector(log2(width*depth/32)-1 downto 0);
|
begin
|
begin
|
addrA_single <= operand_in_sel & operand_addr;
|
addrA_single <= operand_in_sel & operand_addr;
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ramblock : entity mod_sim_exp.tdpramblock_asym
|
ramblock : tdpramblock_asym
|
generic map(
|
generic map(
|
depth => depth,
|
depth => depth,
|
width => width,
|
width => width,
|
device => device
|
device => device
|
)
|
)
|
port map(
|
port map(
|
clk => clk,
|
clk => clk,
|
-- port A 32-bit
|
-- port A 32-bit
|
addrA => addrA_single,
|
addrA => addrA_single,
|
weA => write_operand_i,
|
weA => write_operand_i,
|
dinA => operand_in,
|
dinA => operand_in,
|
doutA => result_out,
|
doutA => result_out,
|
-- port B (width)-bit
|
-- port B (width)-bit
|
addrB => mult_op_sel,
|
addrB => mult_op_sel,
|
weB => write_result,
|
weB => write_result,
|
dinB => result_in,
|
dinB => result_in,
|
doutB => operand_out
|
doutB => operand_out
|
);
|
);
|
end generate;
|
end generate;
|
|
|
multiple_full_blocks : if (width > RAMblock_maxwidth) generate
|
multiple_full_blocks : if (width > RAMblock_maxwidth) generate
|
-- signals for multiple blocks
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-- signals for multiple blocks
|
type wordsplit is array (nrRAMblocks_full downto 0) of std_logic_vector(31 downto 0);
|
type wordsplit is array (nrRAMblocks_full downto 0) of std_logic_vector(31 downto 0);
|
signal doutA_RAM : wordsplit;
|
signal doutA_RAM : wordsplit;
|
signal addrA : std_logic_vector(log2(RAMblock_maxwidth*depth/32)-1 downto 0);
|
signal addrA : std_logic_vector(log2(RAMblock_maxwidth*depth/32)-1 downto 0);
|
signal weA_RAM : std_logic_vector(nrRAMblocks_full-1 downto 0);
|
signal weA_RAM : std_logic_vector(nrRAMblocks_full-1 downto 0);
|
begin
|
begin
|
ramblocks_full : for i in 0 to nrRAMblocks_full generate
|
ramblocks_full : for i in 0 to nrRAMblocks_full generate
|
-- port A signals
|
-- port A signals
|
addrA <= operand_in_sel & operand_addr(log2(RAMblock_maxwidth/32)-1 downto 0);
|
addrA <= operand_in_sel & operand_addr(log2(RAMblock_maxwidth/32)-1 downto 0);
|
|
|
full_ones : if (i < nrRAMblocks_full) generate
|
full_ones : if (i < nrRAMblocks_full) generate
|
ramblock_full : entity mod_sim_exp.tdpramblock_asym
|
ramblock_full : tdpramblock_asym
|
generic map(
|
generic map(
|
depth => depth,
|
depth => depth,
|
width => RAMblock_maxwidth,
|
width => RAMblock_maxwidth,
|
device => device
|
device => device
|
)
|
)
|
port map(
|
port map(
|
clk => clk,
|
clk => clk,
|
-- port A 32-bit
|
-- port A 32-bit
|
addrA => addrA,
|
addrA => addrA,
|
weA => weA_RAM(i),
|
weA => weA_RAM(i),
|
dinA => operand_in,
|
dinA => operand_in,
|
doutA => doutA_RAM(i),
|
doutA => doutA_RAM(i),
|
-- port B (width)-bit
|
-- port B (width)-bit
|
addrB => mult_op_sel,
|
addrB => mult_op_sel,
|
weB => write_result,
|
weB => write_result,
|
dinB => result_in((i+1)*RAMblock_maxwidth-1 downto i*RAMblock_maxwidth),
|
dinB => result_in((i+1)*RAMblock_maxwidth-1 downto i*RAMblock_maxwidth),
|
doutB => operand_out((i+1)*RAMblock_maxwidth-1 downto i*RAMblock_maxwidth)
|
doutB => operand_out((i+1)*RAMblock_maxwidth-1 downto i*RAMblock_maxwidth)
|
);
|
);
|
-- weA, weB
|
-- weA, weB
|
process (write_operand_i, operand_addr)
|
process (write_operand_i, operand_addr)
|
begin
|
begin
|
if operand_addr(log2(width/32)-1 downto log2(RAMblock_maxwidth/32)) = conv_std_logic_vector(i,RAMselect_aw) then
|
if operand_addr(log2(width/32)-1 downto log2(RAMblock_maxwidth/32)) = conv_std_logic_vector(i,RAMselect_aw) then
|
weA_RAM(i) <= write_operand_i;
|
weA_RAM(i) <= write_operand_i;
|
else
|
else
|
weA_RAM(i) <= '0';
|
weA_RAM(i) <= '0';
|
end if;
|
end if;
|
end process;
|
end process;
|
only_once : if (i = 0) generate
|
only_once : if (i = 0) generate
|
-- port A read mux
|
-- port A read mux
|
only_full_blocks : if (RAMblock_part = 0) generate
|
only_full_blocks : if (RAMblock_part = 0) generate
|
result_out <= doutA_RAM(conv_integer(operand_addr(log2(width/32)-1 downto log2(RAMblock_maxwidth/32))))
|
result_out <= doutA_RAM(conv_integer(operand_addr(log2(width/32)-1 downto log2(RAMblock_maxwidth/32))))
|
when (conv_integer(operand_addr(log2(width/32)-1 downto log2(RAMblock_maxwidth/32)))<nrRAMblocks_full)
|
when (conv_integer(operand_addr(log2(width/32)-1 downto log2(RAMblock_maxwidth/32)))<nrRAMblocks_full)
|
else (others=>'0');
|
else (others=>'0');
|
end generate;
|
end generate;
|
with_extra_part : if (RAMblock_part /= 0) generate
|
with_extra_part : if (RAMblock_part /= 0) generate
|
result_out <= doutA_RAM(conv_integer(operand_addr(log2(width/32)-1 downto log2(RAMblock_maxwidth/32))))
|
result_out <= doutA_RAM(conv_integer(operand_addr(log2(width/32)-1 downto log2(RAMblock_maxwidth/32))))
|
when (conv_integer(operand_addr(log2(width/32)-1 downto log2(RAMblock_maxwidth/32)))<nrRAMblocks_full+1)
|
when (conv_integer(operand_addr(log2(width/32)-1 downto log2(RAMblock_maxwidth/32)))<nrRAMblocks_full+1)
|
else (others=>'0');
|
else (others=>'0');
|
end generate;
|
end generate;
|
end generate;
|
end generate;
|
end generate;
|
end generate;
|
|
|
optional_part : if (i = nrRAMblocks_full) and (RAMblock_part /= 0) generate
|
optional_part : if (i = nrRAMblocks_full) and (RAMblock_part /= 0) generate
|
-- signals for part
|
-- signals for part
|
signal addrA_part : std_logic_vector(log2(RAMblock_part_width*depth/32)-1 downto 0);
|
signal addrA_part : std_logic_vector(log2(RAMblock_part_width*depth/32)-1 downto 0);
|
signal weA_part : std_logic;
|
signal weA_part : std_logic;
|
begin
|
begin
|
addrA_part <= operand_in_sel & operand_addr(log2(RAMblock_part_width/32)-1 downto 0);
|
addrA_part <= operand_in_sel & operand_addr(log2(RAMblock_part_width/32)-1 downto 0);
|
ramblock_part : entity mod_sim_exp.tdpramblock_asym
|
ramblock_part : tdpramblock_asym
|
generic map(
|
generic map(
|
depth => depth,
|
depth => depth,
|
width => RAMblock_part_width,
|
width => RAMblock_part_width,
|
device => device
|
device => device
|
)
|
)
|
port map(
|
port map(
|
clk => clk,
|
clk => clk,
|
-- port A 32-bit
|
-- port A 32-bit
|
addrA => addrA_part,
|
addrA => addrA_part,
|
weA => weA_part,
|
weA => weA_part,
|
dinA => operand_in,
|
dinA => operand_in,
|
doutA => doutA_RAM(i),
|
doutA => doutA_RAM(i),
|
-- port B (width)-bit
|
-- port B (width)-bit
|
addrB => mult_op_sel,
|
addrB => mult_op_sel,
|
weB => write_result,
|
weB => write_result,
|
dinB => result_in(width-1 downto i*RAMblock_maxwidth),
|
dinB => result_in(width-1 downto i*RAMblock_maxwidth),
|
doutB => operand_out(width-1 downto i*RAMblock_maxwidth)
|
doutB => operand_out(width-1 downto i*RAMblock_maxwidth)
|
);
|
);
|
-- weA, weB part
|
-- weA, weB part
|
process (write_operand_i, operand_addr)
|
process (write_operand_i, operand_addr)
|
begin
|
begin
|
if operand_addr(log2(width/32)-1 downto log2(RAMblock_maxwidth/32)) = conv_std_logic_vector(i,RAMselect_aw) then
|
if operand_addr(log2(width/32)-1 downto log2(RAMblock_maxwidth/32)) = conv_std_logic_vector(i,RAMselect_aw) then
|
weA_part <= write_operand_i;
|
weA_part <= write_operand_i;
|
else
|
else
|
weA_part <= '0';
|
weA_part <= '0';
|
end if;
|
end if;
|
end process;
|
end process;
|
end generate;
|
end generate;
|
end generate;
|
end generate;
|
end generate;
|
end generate;
|
|
|
end Behavioral;
|
end Behavioral;
|
|
|
