| Line 1... |
Line 1... |
------------------------------------------------------------------------------------
|
----------------------------------------------------------------------
|
--
|
---- register_1b ----
|
-- Geoffrey Ottoy - DraMCo research group
|
---- ----
|
--
|
---- This file is part of the ----
|
-- Module Name: register_1b.vhd / entity register_1b
|
---- Modular Simultaneous Exponentiation Core project ----
|
--
|
---- http://www.opencores.org/cores/mod_sim_exp/ ----
|
-- Last Modified: 24/11/2011
|
---- ----
|
--
|
---- Description ----
|
-- Description: 1 bit register
|
---- 1 bit register ----
|
--
|
---- used in montgommery multiplier systolic array stages ----
|
--
|
---- ----
|
-- Dependencies: LDCE
|
---- Dependencies: none ----
|
--
|
---- ----
|
-- Revision:
|
---- Authors: ----
|
-- Revision 1.00 - Architecture
|
---- - Geoffrey Ottoy, DraMCo research group ----
|
-- Revision 0.01 - File Created
|
---- - Jonas De Craene, JonasDC@opencores.org ----
|
--
|
---- ----
|
--
|
----------------------------------------------------------------------
|
------------------------------------------------------------------------------------
|
---- ----
|
--
|
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
|
-- NOTICE:
|
---- ----
|
--
|
---- This source file may be used and distributed without ----
|
-- Copyright DraMCo research group. 2011. This code may be contain portions patented
|
---- restriction provided that this copyright statement is not ----
|
-- by other third parties!
|
---- removed from the file and that any derivative work contains ----
|
--
|
---- the original copyright notice and the associated disclaimer. ----
|
------------------------------------------------------------------------------------
|
---- ----
|
library IEEE;
|
---- This source file is free software; you can redistribute it ----
|
use IEEE.STD_LOGIC_1164.ALL;
|
---- and/or modify it under the terms of the GNU Lesser General ----
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
---- Public License as published by the Free Software Foundation; ----
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
---- either version 2.1 of the License, or (at your option) any ----
|
|
---- later version. ----
|
|
---- ----
|
|
---- This source is distributed in the hope that it will be ----
|
|
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
|
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
|
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
|
---- details. ----
|
|
---- ----
|
|
---- You should have received a copy of the GNU Lesser General ----
|
|
---- Public License along with this source; if not, download it ----
|
|
---- from http://www.opencores.org/lgpl.shtml ----
|
|
---- ----
|
|
----------------------------------------------------------------------
|
|
|
|
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
use ieee.std_logic_arith.all;
|
|
use ieee.std_logic_unsigned.all;
|
|
|
---- Uncomment the following library declaration if instantiating
|
-- Xilinx primitives used
|
---- any Xilinx primitives in this code.
|
|
library UNISIM;
|
library UNISIM;
|
use UNISIM.VComponents.all;
|
use UNISIM.VComponents.all;
|
|
|
|
|
entity register_1b is
|
entity register_1b is
|
port(core_clk : in STD_LOGIC;
|
port(
|
ce : in STD_LOGIC;
|
core_clk : in std_logic;
|
reset : in STD_LOGIC;
|
ce : in std_logic;
|
din : in STD_LOGIC;
|
reset : in std_logic;
|
dout : out STD_LOGIC
|
din : in std_logic;
|
|
dout : out std_logic
|
);
|
);
|
end register_1b;
|
end register_1b;
|
|
|
|
|
architecture Structural of register_1b is
|
architecture Structural of register_1b is
|
signal dout_i : std_logic;
|
signal dout_i : std_logic;
|
begin
|
begin
|
|
|
dout <= dout_i;
|
dout <= dout_i;
|
|
|
FDCE_inst : FDCE
|
FDCE_inst : FDCE
|
generic map (
|
generic map (
|
INIT => '0') -- Initial value of latch ('0' or '1')
|
INIT => '0' -- Initial value of latch ('0' or '1')
|
|
)
|
port map (
|
port map (
|
Q => dout_i, -- Data output
|
Q => dout_i, -- Data output
|
CLR => reset, -- Asynchronous clear/reset input
|
CLR => reset, -- Asynchronous clear/reset input
|
D => din, -- Data input
|
D => din, -- Data input
|
C => core_clk, -- Gate input
|
C => core_clk, -- Gate input
|
