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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [register_n.vhd] - Diff between revs 3 and 7

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----  This file is part of the                                    ----
----  This file is part of the                                    ----
----    Modular Simultaneous Exponentiation Core project          ---- 
----    Modular Simultaneous Exponentiation Core project          ---- 
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
----                                                              ---- 
----                                                              ---- 
----  Description                                                 ---- 
----  Description                                                 ---- 
----    n bit register                                            ----
----    n bit register with active high asynchronious reset and ce----
----    used in montgommery multiplier systolic array stages      ----            
----    used in montgommery multiplier systolic array stages      ----            
----                                                              ---- 
----                                                              ---- 
----  Dependencies: none                                          ----
----  Dependencies: none                                          ----
----                                                              ----
----                                                              ----
----  Authors:                                                    ----
----  Authors:                                                    ----
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library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all;
 
 
-- Xilinx primitives used
-- n-bit register with asynchronous reset and clock enable
library UNISIM;
 
use UNISIM.VComponents.all;
 
 
 
 
 
entity register_n is
entity register_n is
  generic(
  generic(
    n : integer := 4
    n : integer := 4
  );
  );
  port(
  port(
    core_clk : in  std_logic;
    core_clk : in  std_logic; -- clock input
    ce       : in  std_logic;
    ce       : in  std_logic; -- clock enable (active high)
    reset    : in  std_logic;
    reset    : in  std_logic; -- reset (active high)
    din      : in  std_logic_vector((n-1) downto 0);
    din      : in  std_logic_vector((n-1) downto 0);  -- data in (n-bit)
    dout     : out std_logic_vector((n-1) downto 0)
    dout     : out std_logic_vector((n-1) downto 0)   -- data out (n-bit)
  );
  );
end register_n;
end register_n;
 
 
 
 
architecture Structural of register_n is
architecture Behavorial of register_n is
        signal dout_i : std_logic_vector((n-1) downto 0) := (others => '0');
 
begin
begin
 
         -- process for n-bit register
 
  reg_nb : process (reset, ce, core_clk, din)
 
  begin
 
    if reset='1' then -- asynchronous active high reset
 
      dout <= (others=>'0');
 
    else
 
      if rising_edge(core_clk) then -- clock in data on rising edge
 
        if ce='1' then  -- active high clock enable to clock in data
 
          dout <= din;
 
        end if;
 
      end if;
 
    end if;
 
  end process;
 
 
        dout <= dout_i;
end Behavorial;
 
 
  N_REGS : for i in 0 to n-1 generate
 
    FDCE_inst : FDCE
 
    generic map (
 
      INIT => '0'       -- Initial value of latch ('0' or '1')
 
    )
 
    port map (
 
      Q   => dout_i(i), -- Data output
 
      CLR => reset,     -- Asynchronous clear/reset input
 
      D   => din(i),    -- Data input
 
      C   => core_clk,  -- Gate input
 
      CE  => ce         -- Gate enable input
 
    );
 
  end generate;
 
 
 
end Structural;
 
 
 
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