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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [standard_cell_block.vhd] - Diff between revs 3 and 17

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----  This file is part of the                                    ----
----  This file is part of the                                    ----
----    Modular Simultaneous Exponentiation Core project          ---- 
----    Modular Simultaneous Exponentiation Core project          ---- 
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
----                                                              ---- 
----                                                              ---- 
----  Description                                                 ---- 
----  Description                                                 ---- 
----    a block of [width] cell_1b cells for use in the           ----
----    a block of (width) cell_1b cells for use in the           ----
----    montgommery multiplier systolic array                     ----
----    montgommery multiplier systolic array                     ----
----                                                              ----
----                                                              ----
----  Dependencies:                                               ----
----  Dependencies:                                               ----
----    - cell_1b                                                 ----
----    - cell_1b                                                 ----
----                                                              ----
----                                                              ----
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use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all;
 
 
library mod_sim_exp;
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
 
 
-- a standard cell block of (width)-bit for the montgommery multiplier 
 
-- systolic array
entity standard_cell_block is
entity standard_cell_block is
  generic (
  generic (
    width : integer := 16
    width : integer := 16
  );
  );
  port (
  port (
 
    -- modulus and y operand input (width)-bit
    my   : in  std_logic_vector((width-1) downto 0);
    my   : in  std_logic_vector((width-1) downto 0);
    y    : in  std_logic_vector((width-1) downto 0);
    y    : in  std_logic_vector((width-1) downto 0);
    m    : in  std_logic_vector((width-1) downto 0);
    m    : in  std_logic_vector((width-1) downto 0);
 
    -- q and x operand input (serial input)
    x    : in  std_logic;
    x    : in  std_logic;
    q    : in  std_logic;
    q    : in  std_logic;
 
    -- previous result in (width)-bit
    a    : in  std_logic_vector((width-1) downto 0);
    a    : in  std_logic_vector((width-1) downto 0);
 
    -- carry in and out
    cin  : in std_logic;
    cin  : in std_logic;
    cout : out std_logic;
    cout : out std_logic;
 
    -- result out (width)-bit
    r    : out  std_logic_vector((width-1) downto 0)
    r    : out  std_logic_vector((width-1) downto 0)
  );
  );
end standard_cell_block;
end standard_cell_block;
 
 
 
 
architecture Structural of standard_cell_block is
architecture Structural of standard_cell_block is
 
  -- vector for the carry bits
        signal carry : std_logic_vector(width downto 0);
        signal carry : std_logic_vector(width downto 0);
begin
begin
 
 
 
        -- carry in
        carry(0) <= cin;
        carry(0) <= cin;
 
 
 
        -- structure of (width) 1-bit cells
  cell_block : for i in 0 to (width-1) generate
  cell_block : for i in 0 to (width-1) generate
    cells : cell_1b
    cells : cell_1b
    port map(
    port map(
      my   => my(i),
      my   => my(i),
      y    => y(i),
      y    => y(i),
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      cout => carry(i+1),
      cout => carry(i+1),
      r    => r(i)
      r    => r(i)
    );
    );
  end generate;
  end generate;
 
 
 
  -- carry out
        cout <= carry(width);
        cout <= carry(width);
end Structural;
end Structural;
 
 
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