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---- This file is part of the ----
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---- This file is part of the ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- ----
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---- ----
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---- Description ----
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---- Description ----
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---- a block of [width] cell_1b cells for use in the ----
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---- a block of (width) cell_1b cells for use in the ----
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---- montgommery multiplier systolic array ----
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---- montgommery multiplier systolic array ----
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---- ----
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---- ----
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---- Dependencies: ----
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---- Dependencies: ----
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---- - cell_1b ----
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---- - cell_1b ----
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---- ----
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---- ----
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Line 49... |
use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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library mod_sim_exp;
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library mod_sim_exp;
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use mod_sim_exp.mod_sim_exp_pkg.all;
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use mod_sim_exp.mod_sim_exp_pkg.all;
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-- a standard cell block of (width)-bit for the montgommery multiplier
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-- systolic array
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entity standard_cell_block is
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entity standard_cell_block is
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generic (
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generic (
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width : integer := 16
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width : integer := 16
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);
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);
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port (
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port (
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-- modulus and y operand input (width)-bit
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my : in std_logic_vector((width-1) downto 0);
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my : in std_logic_vector((width-1) downto 0);
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y : in std_logic_vector((width-1) downto 0);
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y : in std_logic_vector((width-1) downto 0);
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m : in std_logic_vector((width-1) downto 0);
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m : in std_logic_vector((width-1) downto 0);
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-- q and x operand input (serial input)
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x : in std_logic;
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x : in std_logic;
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q : in std_logic;
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q : in std_logic;
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-- previous result in (width)-bit
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a : in std_logic_vector((width-1) downto 0);
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a : in std_logic_vector((width-1) downto 0);
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-- carry in and out
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cin : in std_logic;
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cin : in std_logic;
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cout : out std_logic;
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cout : out std_logic;
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-- result out (width)-bit
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r : out std_logic_vector((width-1) downto 0)
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r : out std_logic_vector((width-1) downto 0)
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);
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);
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end standard_cell_block;
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end standard_cell_block;
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architecture Structural of standard_cell_block is
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architecture Structural of standard_cell_block is
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-- vector for the carry bits
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signal carry : std_logic_vector(width downto 0);
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signal carry : std_logic_vector(width downto 0);
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begin
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begin
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-- carry in
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carry(0) <= cin;
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carry(0) <= cin;
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-- structure of (width) 1-bit cells
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cell_block : for i in 0 to (width-1) generate
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cell_block : for i in 0 to (width-1) generate
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cells : cell_1b
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cells : cell_1b
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port map(
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port map(
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my => my(i),
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my => my(i),
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y => y(i),
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y => y(i),
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| Line 89... |
Line 98... |
cout => carry(i+1),
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cout => carry(i+1),
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r => r(i)
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r => r(i)
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);
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);
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end generate;
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end generate;
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-- carry out
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cout <= carry(width);
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cout <= carry(width);
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end Structural;
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end Structural;
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No newline at end of file
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No newline at end of file
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