URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [sys_pipeline.vhd] - Diff between revs 30 and 31

Rev 30	Rev 31
Line 153...	Line 153...
`a_msb_stage(i-1) <= a_0_stage(i);`	`a_msb_stage(i-1) <= a_0_stage(i);`
`end generate;`	`end generate;`

`-- first cell logic`	`-- first cell logic`
`--------------------`	`--------------------`
`my0 <= m_i(0) xor y_i(0); -- m0 + y0`	`first_stage : sys_first_cell_logic`
`-- stage 0 connections`
`my_cin_stage(0) <= m_i(0) and y_i(0); -- m0 + y0 carry`
`xin_stage(0) <= xi;`
`qin_stage(0) <= (xi and y_i(0)) xor a_0_stage(0);`
`cin_stage(0) <= my0_mux_result and a_0_stage(0);`
`red_cin_stage(0) <= '1'; -- add 1 for 2s complement`
`start_stage(0) <= start;`

`my0_mux : cell_1b_mux`
`port map(`	`port map(`
`my => my0,`	`m0 => m_i(0),`
`m => m_i(0),`	`y0 => y_i(0),`
`y => y_i(0),`	`my_cout => my_cin_stage(0),`
`x => xin_stage(0),`	`xi => xi,`
`q => qin_stage(0),`	`xout => xin_stage(0),`
`result => my0_mux_result`	`qout => qin_stage(0),`
	`cout => cin_stage(0),`
	`a_0 => a_0_stage(0),`
	`red_cout => red_cin_stage(0)`
`);`	`);`

	`start_stage(0) <= start;`
`next_x <= done_stage(0);`	`next_x <= done_stage(0);`

`-- last cell logic`	`-- last cell logic`
`-------------------`	`-------------------`
`last_cell : sys_last_cell_logic`	`last_cell : sys_last_cell_logic`