| Line 101... |
Line 101... |
signal red_cout_stage : std_logic_vector((t-1) downto 0);
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signal red_cout_stage : std_logic_vector((t-1) downto 0);
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signal start_stage : std_logic_vector((t-1) downto 0);
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signal start_stage : std_logic_vector((t-1) downto 0);
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signal done_stage : std_logic_vector((t-1) downto 0);
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signal done_stage : std_logic_vector((t-1) downto 0);
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signal r_sel : std_logic;
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signal r_sel : std_logic;
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-- first cell signals
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-- mid end signals
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signal my0_mux_result : std_logic;
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signal a_0_midend : std_logic;
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signal my0 : std_logic;
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signal r_sel_midend : std_logic;
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-- mid start signals
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signal my_cout_midstart : std_logic;
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signal xout_midstart : std_logic;
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signal qout_midstart : std_logic;
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signal cout_midstart : std_logic;
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signal red_cout_midstart : std_logic;
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-- end signals
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signal r_sel_end : std_logic;
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begin
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begin
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m_i <= '0' & m;
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m_i <= '0' & m;
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y_i <= '0' & y;
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y_i <= '0' & y;
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| Line 140... |
Line 149... |
r_sel => r_sel,
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r_sel => r_sel,
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r => r(((i+1)*s)-1 downto (i*s))
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r => r(((i+1)*s)-1 downto (i*s))
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);
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);
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end generate;
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end generate;
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-- link stages to eachother
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stage_connect : for i in 1 to (t-1) generate
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my_cin_stage(i) <= my_cout_stage(i-1);
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cin_stage(i) <= cout_stage(i-1);
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xin_stage(i) <= xout_stage(i-1);
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qin_stage(i) <= qout_stage(i-1);
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red_cin_stage(i) <= red_cout_stage(i-1);
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start_stage(i) <= done_stage(i-1);
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a_msb_stage(i-1) <= a_0_stage(i);
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end generate;
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-- first cell logic
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-- first cell logic
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--------------------
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--------------------
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first_stage : sys_first_cell_logic
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first_cell : sys_first_cell_logic
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port map (
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port map (
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m0 => m_i(0),
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m0 => m_i(0),
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y0 => y_i(0),
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y0 => y_i(0),
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my_cout => my_cin_stage(0),
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my_cout => my_cin_stage(0),
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xi => xi,
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xi => xi,
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| Line 166... |
Line 166... |
cout => cin_stage(0),
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cout => cin_stage(0),
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a_0 => a_0_stage(0),
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a_0 => a_0_stage(0),
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red_cout => red_cin_stage(0)
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red_cout => red_cin_stage(0)
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);
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);
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start_stage(0) <= start;
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-- only start first stage if lower part is used
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next_x <= done_stage(0);
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with p_sel select
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start_stage(0) <= '0' when "10",
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start when others;
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with p_sel select
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next_x <= done_stage(tl) when "10",
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done_stage(0) when others;
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-- link lower stages to eachother
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stage_connect_l : for i in 1 to (tl-1) generate
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my_cin_stage(i) <= my_cout_stage(i-1);
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cin_stage(i) <= cout_stage(i-1);
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xin_stage(i) <= xout_stage(i-1);
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qin_stage(i) <= qout_stage(i-1);
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red_cin_stage(i) <= red_cout_stage(i-1);
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start_stage(i) <= done_stage(i-1);
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a_msb_stage(i-1) <= a_0_stage(i);
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end generate;
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-- mid end logic
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-----------------
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mid_end_cell : sys_last_cell_logic
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port map (
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core_clk => core_clk,
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reset => reset,
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a_0 => a_0_midend,
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cin => cout_stage(tl-1),
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red_cin => red_cout_stage(tl-1),
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r_sel => r_sel_midend,
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start => done_stage(tl-1)
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);
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--muxes for midend signals
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with p_sel select
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a_msb_stage(tl-1) <= a_0_midend when "01",
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a_0_stage(tl) when others;
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-- mid start logic
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-------------------
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mid_start_logic : sys_first_cell_logic
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port map (
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m0 => m_i(tl*s),
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y0 => y_i(tl*s),
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my_cout => my_cout_midstart,
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xi => xi,
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xout => xout_midstart,
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qout => qout_midstart,
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cout => cout_midstart,
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a_0 => a_0_stage(tl),
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red_cout => red_cout_midstart
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);
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-- only start stage tl if only higher part is used
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with p_sel select
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start_stage(tl) <= start when "10",
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done_stage(tl-1) when "11",
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'0' when others;
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with p_sel select
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my_cin_stage(tl) <= my_cout_midstart when "10",
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my_cout_stage(tl-1) when others;
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with p_sel select
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xin_stage(tl) <= xout_midstart when "10",
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xout_stage(tl-1) when others;
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with p_sel select
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qin_stage(tl) <= qout_midstart when "10",
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qout_stage(tl-1) when others;
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with p_sel select
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cin_stage(tl) <= cout_midstart when "10",
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cout_stage(tl-1) when others;
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with p_sel select
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red_cin_stage(tl) <= red_cout_midstart when "10",
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red_cout_stage(tl-1) when others;
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-- link higher stages to eachother
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stage_connect_h : for i in (tl+1) to (t-1) generate
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my_cin_stage(i) <= my_cout_stage(i-1);
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cin_stage(i) <= cout_stage(i-1);
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xin_stage(i) <= xout_stage(i-1);
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qin_stage(i) <= qout_stage(i-1);
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red_cin_stage(i) <= red_cout_stage(i-1);
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start_stage(i) <= done_stage(i-1);
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a_msb_stage(i-1) <= a_0_stage(i);
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end generate;
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-- last cell logic
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-- last cell logic
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-------------------
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-------------------
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last_cell : sys_last_cell_logic
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last_cell : sys_last_cell_logic
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port map (
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port map (
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core_clk => core_clk,
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core_clk => core_clk,
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reset => reset,
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reset => reset,
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a_0 => a_msb_stage(t-1),
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a_0 => a_msb_stage(t-1),
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cin => cout_stage(t-1),
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cin => cout_stage(t-1),
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red_cin => red_cout_stage(t-1),
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red_cin => red_cout_stage(t-1),
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r_sel => r_sel,
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r_sel => r_sel_end,
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start => done_stage(t-1)
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start => done_stage(t-1)
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);
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);
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with p_sel select
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r_sel <= r_sel_midend when "01",
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r_sel_end when others;
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end Structural;
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end Structural;
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No newline at end of file
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No newline at end of file
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