Subversion Repositories mod_sim_exp

  constant s : integer := n/t;

  constant s : integer := n/t;

  signal m_i           : std_logic_vector(n downto 0);

  signal m_i           : std_logic_vector(n downto 0);

  signal y_i           : std_logic_vector(n downto 0);

  signal y_i           : std_logic_vector(n downto 0);

  -- systolic stages signals

  -- systolic stages signals

  signal my_cin_stage  : std_logic_vector((t-1) downto 0);

  signal my_cin_stage  : std_logic_vector((t-1) downto 0);

  signal my_cout_stage : std_logic_vector((t-1) downto 0);

  signal my_cout_stage : std_logic_vector((t-1) downto 0);

  signal xin_stage     : std_logic_vector((t-1) downto 0);

  signal xin_stage     : std_logic_vector((t-1) downto 0);

  signal cout_stage    : std_logic_vector((t-1) downto 0);

  signal cout_stage    : std_logic_vector((t-1) downto 0);

  signal red_cin_stage : std_logic_vector((t-1) downto 0);

  signal red_cin_stage : std_logic_vector((t-1) downto 0);

  signal red_cout_stage : std_logic_vector((t-1) downto 0);

  signal red_cout_stage : std_logic_vector((t-1) downto 0);

  signal start_stage   : std_logic_vector((t-1) downto 0);

  signal start_stage   : std_logic_vector((t-1) downto 0);

  signal done_stage    : std_logic_vector((t-1) downto 0);

  signal done_stage    : std_logic_vector((t-1) downto 0);

  -- mid end signals

  -- mid end signals

  signal a_0_midend : std_logic;

  signal a_0_midend : std_logic;

  signal r_sel_midend : std_logic;

  signal r_sel_midend : std_logic;

      red_cin  => red_cin_stage(i),

      red_cin  => red_cin_stage(i),

      red_cout => red_cout_stage(i),

      red_cout => red_cout_stage(i),

      start    => start_stage(i),

      start    => start_stage(i),

      reset    => reset,

      reset    => reset,

      done     => done_stage(i),

      done     => done_stage(i),

      r        => r(((i+1)*s)-1 downto (i*s))

      r        => r(((i+1)*s)-1 downto (i*s))

    );

    );

  end generate;

  end generate;

  -- first cell logic

  -- first cell logic

  --------------------

  --------------------

  first_cell : sys_first_cell_logic

  first_cell : sys_first_cell_logic

  port map (

  port map (

    m0       => m_i(0),

    m0       => m_i(0),

    xin_stage(i) <= xout_stage(i-1);

    xin_stage(i) <= xout_stage(i-1);

    qin_stage(i) <= qout_stage(i-1);

    qin_stage(i) <= qout_stage(i-1);

    red_cin_stage(i) <= red_cout_stage(i-1);

    red_cin_stage(i) <= red_cout_stage(i-1);

    start_stage(i) <= done_stage(i-1);

    start_stage(i) <= done_stage(i-1);

    a_msb_stage(i-1) <= a_0_stage(i);

    a_msb_stage(i-1) <= a_0_stage(i);

  end generate;

  end generate;

  -- mid end logic

  -- mid end logic

  -----------------

  -----------------

  mid_end_cell : sys_last_cell_logic

  mid_end_cell : sys_last_cell_logic

  port map (

  port map (

    xin_stage(i) <= xout_stage(i-1);

    xin_stage(i) <= xout_stage(i-1);

    qin_stage(i) <= qout_stage(i-1);

    qin_stage(i) <= qout_stage(i-1);

    red_cin_stage(i) <= red_cout_stage(i-1);

    red_cin_stage(i) <= red_cout_stage(i-1);

    start_stage(i) <= done_stage(i-1);

    start_stage(i) <= done_stage(i-1);

    a_msb_stage(i-1) <= a_0_stage(i);

    a_msb_stage(i-1) <= a_0_stage(i);

  end generate;

  end generate;

  -- last cell logic

  -- last cell logic

  -------------------

  -------------------

  last_cell : sys_last_cell_logic

  last_cell : sys_last_cell_logic

  port map (

  port map (

    r_sel    => r_sel_end,

    r_sel    => r_sel_end,

    start    => done_stage(t-1)

    start    => done_stage(t-1)

  );

  );

  with p_sel select

  with p_sel select

             r_sel_end when others;

             r_sel_end when others;

end Structural;

end Structural;

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