| Line 56... |
Line 56... |
-- the pipelined systolic array for a montgommery multiplier
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-- the pipelined systolic array for a montgommery multiplier
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-- contains a structural description of the pipeline using the systolic stages
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-- contains a structural description of the pipeline using the systolic stages
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entity sys_pipeline is
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entity sys_pipeline is
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generic(
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generic(
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n : integer := 1536; -- width of the operands (# bits)
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n : integer := 1536; -- width of the operands (# bits)
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t : integer := 192; -- total number of stages (divider of n) >= 2
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t : integer := 192; -- total number of stages (minimum 2)
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tl : integer := 64 -- lower number of stages (best take t = sqrt(n))
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tl : integer := 64; -- lower number of stages (minimum 1)
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split : boolean := true -- if true the pipeline wil be split in 2 parts,
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-- if false there are no lower stages, only t counts
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);
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);
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port(
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port(
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-- clock input
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-- clock input
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core_clk : in std_logic;
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core_clk : in std_logic;
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-- modulus and y opperand input (n)-bit
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-- modulus and y opperand input (n)-bit
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| Line 80... |
Line 82... |
end sys_pipeline;
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end sys_pipeline;
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architecture Structural of sys_pipeline is
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architecture Structural of sys_pipeline is
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constant s : integer := n/t;
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constant s : integer := n/t;
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signal m_i : std_logic_vector(n downto 0);
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signal m_i : std_logic_vector(n downto 0);
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signal y_i : std_logic_vector(n downto 0);
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signal y_i : std_logic_vector(n downto 0);
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signal r_sel_l : std_logic;
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signal r_sel_h : std_logic;
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-- systolic stages signals
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-- systolic stages signals
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signal my_cin_stage : std_logic_vector((t-1) downto 0);
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signal my_cin_stage : std_logic_vector((t-1) downto 0);
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signal my_cout_stage : std_logic_vector((t-1) downto 0);
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signal my_cout_stage : std_logic_vector((t-1) downto 0);
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signal xin_stage : std_logic_vector((t-1) downto 0);
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signal xin_stage : std_logic_vector((t-1) downto 0);
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| Line 103... |
Line 102... |
signal red_cout_stage : std_logic_vector((t-1) downto 0);
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signal red_cout_stage : std_logic_vector((t-1) downto 0);
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signal start_stage : std_logic_vector((t-1) downto 0);
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signal start_stage : std_logic_vector((t-1) downto 0);
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signal done_stage : std_logic_vector((t-1) downto 0);
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signal done_stage : std_logic_vector((t-1) downto 0);
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signal r_sel_stage : std_logic_vector((t-1) downto 0);
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signal r_sel_stage : std_logic_vector((t-1) downto 0);
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-- mid end signals
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-- end logic signals
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signal r_sel_end : std_logic;
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-- signals needed if pipeline is split
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---------------------------------------
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signal r_sel_l : std_logic;
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signal r_sel_h : std_logic;
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-- mid end logic signals
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signal a_0_midend : std_logic;
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signal a_0_midend : std_logic;
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signal r_sel_midend : std_logic;
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signal r_sel_midend : std_logic;
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-- mid start signals
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-- mid start logic signals
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signal my_cout_midstart : std_logic;
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signal my_cout_midstart : std_logic;
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signal xout_midstart : std_logic;
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signal xout_midstart : std_logic;
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signal qout_midstart : std_logic;
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signal qout_midstart : std_logic;
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signal cout_midstart : std_logic;
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signal cout_midstart : std_logic;
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signal red_cout_midstart : std_logic;
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signal red_cout_midstart : std_logic;
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-- end signals
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signal r_sel_end : std_logic;
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begin
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begin
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|
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m_i <= '0' & m;
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m_i <= '0' & m;
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y_i <= '0' & y;
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y_i <= '0' & y;
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| Line 166... |
Line 171... |
cout => cin_stage(0),
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cout => cin_stage(0),
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a_0 => a_0_stage(0),
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a_0 => a_0_stage(0),
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red_cout => red_cin_stage(0)
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red_cout => red_cin_stage(0)
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);
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);
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-- last cell logic
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-------------------
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last_cell : sys_last_cell_logic
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port map (
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core_clk => core_clk,
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reset => reset,
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a_0 => a_msb_stage(t-1),
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cin => cout_stage(t-1),
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red_cin => red_cout_stage(t-1),
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r_sel => r_sel_end,
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start => done_stage(t-1)
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);
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------------------------------------
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-- SINGLE PART PIPELINE CONNECTIONS
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------------------------------------
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single_pipeline : if split=false generate
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-- link stages to eachother
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stage_connect : for i in 1 to (t-1) generate
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my_cin_stage(i) <= my_cout_stage(i-1);
|
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cin_stage(i) <= cout_stage(i-1);
|
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xin_stage(i) <= xout_stage(i-1);
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qin_stage(i) <= qout_stage(i-1);
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red_cin_stage(i) <= red_cout_stage(i-1);
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start_stage(i) <= done_stage(i-1);
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a_msb_stage(i-1) <= a_0_stage(i);
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r_sel_stage(i) <= r_sel_end;
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end generate;
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r_sel_stage(0) <= r_sel_end;
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|
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start_stage(0) <= start;
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next_x <= done_stage(0);
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end generate;
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|
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----------------------------------------
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-- SPLIT PIPELINE CONNECTIONS AND LOGIC
|
|
----------------------------------------
|
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split_pipeline : if split=true generate
|
-- only start first stage if lower part is used
|
-- only start first stage if lower part is used
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with p_sel select
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with p_sel select
|
start_stage(0) <= '0' when "10",
|
start_stage(0) <= '0' when "10",
|
start when others;
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start when others;
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|
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-- select start or midstart stage for requesting new xi bit
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with p_sel select
|
with p_sel select
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next_x <= done_stage(tl) when "10",
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next_x <= done_stage(tl) when "10",
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done_stage(0) when others;
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done_stage(0) when others;
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|
|
-- link lower stages to eachother
|
-- link lower stages to eachother
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| Line 255... |
Line 299... |
a_msb_stage(i-1) <= a_0_stage(i);
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a_msb_stage(i-1) <= a_0_stage(i);
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r_sel_stage(i) <= r_sel_h;
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r_sel_stage(i) <= r_sel_h;
|
end generate;
|
end generate;
|
r_sel_stage(tl) <= r_sel_h;
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r_sel_stage(tl) <= r_sel_h;
|
|
|
-- last cell logic
|
|
-------------------
|
|
last_cell : sys_last_cell_logic
|
|
port map (
|
|
core_clk => core_clk,
|
|
reset => reset,
|
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a_0 => a_msb_stage(t-1),
|
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cin => cout_stage(t-1),
|
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red_cin => red_cout_stage(t-1),
|
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r_sel => r_sel_end,
|
|
start => done_stage(t-1)
|
|
);
|
|
|
|
with p_sel select
|
with p_sel select
|
r_sel_l <= r_sel_midend when "01",
|
r_sel_l <= r_sel_midend when "01",
|
r_sel_end when "11",
|
r_sel_end when "11",
|
'0' when others;
|
'0' when others;
|
|
|
with p_sel select
|
with p_sel select
|
r_sel_h <= '0' when "01",
|
r_sel_h <= '0' when "01",
|
r_sel_end when others;
|
r_sel_end when others;
|
|
end generate;
|
|
|
end Structural;
|
end Structural;
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No newline at end of file
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No newline at end of file
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