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------------------------------------------------------------------------------------
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----------------------------------------------------------------------
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--
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---- x_shift_reg ----
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-- Geoffrey Ottoy - DraMCo research group
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---- ----
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--
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---- This file is part of the ----
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-- Module Name: x_shift_reg.vhd / entity x_shift_reg
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---- Modular Simultaneous Exponentiation Core project ----
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--
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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-- Last Modified: 18/06/2012
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---- ----
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--
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---- Description ----
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-- Description: n-bit shift register with lsb output
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---- 1536 bit shift register with lsb output ----
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--
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---- ----
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--
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---- Dependencies: none ----
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-- Dependencies: none
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---- ----
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--
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---- Authors: ----
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-- Revision:
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---- - Geoffrey Ottoy, DraMCo research group ----
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-- Revision 1.00 - Architecture
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---- - Jonas De Craene, JonasDC@opencores.org ----
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-- Revision 0.01 - File Created
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---- ----
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--
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----------------------------------------------------------------------
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--
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---- ----
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------------------------------------------------------------------------------------
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
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--
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---- ----
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-- NOTICE:
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---- This source file may be used and distributed without ----
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--
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---- restriction provided that this copyright statement is not ----
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-- Copyright DraMCo research group. 2011. This code may be contain portions patented
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---- removed from the file and that any derivative work contains ----
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-- by other third parties!
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---- the original copyright notice and the associated disclaimer. ----
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--
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---- ----
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------------------------------------------------------------------------------------
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---- This source file is free software; you can redistribute it ----
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library IEEE;
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---- and/or modify it under the terms of the GNU Lesser General ----
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use IEEE.STD_LOGIC_1164.ALL;
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---- Public License as published by the Free Software Foundation; ----
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use IEEE.STD_LOGIC_ARITH.ALL;
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---- either version 2.1 of the License, or (at your option) any ----
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- later version. ----
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---- ----
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---- Uncomment the following library declaration if instantiating
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---- This source is distributed in the hope that it will be ----
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---- any Xilinx primitives in this code.
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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--library UNISIM;
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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--use UNISIM.VComponents.all;
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity x_shift_reg is
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entity x_shift_reg is
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generic( n : integer := 1536;
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generic(
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n : integer := 1536;
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t : integer := 48;
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t : integer := 48;
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tl : integer := 16
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tl : integer := 16
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);
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);
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port( clk : in STD_LOGIC;
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port(
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reset : in STD_LOGIC;
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clk : in std_logic;
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x_in : in STD_LOGIC_VECTOR((n-1) downto 0);
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reset : in std_logic;
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load_x : in STD_LOGIC;
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x_in : in std_logic_vector((n-1) downto 0);
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next_x : in STD_LOGIC;
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load_x : in std_logic;
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p_sel : in STD_LOGIC_VECTOR(1 downto 0);
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next_x : in std_logic;
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x_i : out STD_LOGIC
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p_sel : in std_logic_vector(1 downto 0);
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x_i : out std_logic
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);
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);
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end x_shift_reg;
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end x_shift_reg;
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architecture Behavioral of x_shift_reg is
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architecture Behavioral of x_shift_reg is
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signal x_reg_i : std_logic_vector((n-1) downto 0); -- register
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signal x_reg_i : std_logic_vector((n-1) downto 0); -- register
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constant s : integer := n/t; -- nr of stages
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constant s : integer := n/t; -- nr of stages
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constant offset : integer := s*tl; -- calculate startbit pos of higher part of pipeline
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constant offset : integer := s*tl; -- calculate startbit pos of higher part of pipeline
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begin
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begin
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x_i <= x_reg_i(offset) when "10", -- use bit at offset for high part of pipeline
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x_i <= x_reg_i(offset) when "10", -- use bit at offset for high part of pipeline
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x_reg_i(0) when others; -- use LS bit for lower part of pipeline
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x_reg_i(0) when others; -- use LS bit for lower part of pipeline
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end Behavioral;
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end Behavioral;
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