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reset : in std_logic; -- reset, clears register
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reset : in std_logic; -- reset, clears register
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load_x : in std_logic; -- load operand into shift register
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load_x : in std_logic; -- load operand into shift register
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next_x : in std_logic; -- next bit of x
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next_x : in std_logic; -- next bit of x
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p_sel : in std_logic_vector(1 downto 0); -- pipeline selection
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p_sel : in std_logic_vector(1 downto 0); -- pipeline selection
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-- x operand bit out (serial)
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-- x operand bit out (serial)
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x_i : out std_logic
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xi : out std_logic
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);
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);
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end x_shift_reg;
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end x_shift_reg;
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architecture Behavioral of x_shift_reg is
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architecture Behavioral of x_shift_reg is
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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with p_sel select -- pipeline select
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with p_sel select -- pipeline select
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x_i <= x_reg(offset) when "10", -- use bit at offset for high part of pipeline
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xi <= x_reg(offset) when "10", -- use bit at offset for high part of pipeline
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x_reg(0) when others; -- use LS bit for lower part of pipeline
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x_reg(0) when others; -- use LS bit for lower part of pipeline
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end Behavioral;
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end Behavioral;
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