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----------------------------------------------------------------------
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---- msec_ipcore_axilite ----
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---- ----
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---- This file is part of the ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- ----
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---- Description ----
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---- AXI-Lite bus interface for the mod_sim_exp_core. Has a ----
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---- fixed address decoder, address offsets are: ----
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---- ----
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---- M : 0xXXXX0000 ----
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---- OP0 : 0xXXXX1000 ----
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---- OP1 : 0xXXXX2000 ----
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---- OP2 : 0xXXXX3000 ----
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---- OP3 : 0xXXXX4000 ----
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---- FIFO : 0xXXXX5000 ----
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---- Control : 0xXXXX6000 ----
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---- ----
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---- only the XXXX part of the address can be chosen freely ----
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---- ----
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---- Dependencies: ----
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---- - mod_sim_exp_core ----
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---- ----
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---- Authors: ----
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---- - Geoffrey Ottoy, DraMCo research group ----
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---- - Jonas De Craene, JonasDC@opencores.org ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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library mod_sim_exp;
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use mod_sim_exp.mod_sim_exp_pkg;
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------------------------------------------------------------------------------
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-- Entity section
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------------------------------------------------------------------------------
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-- Definition of Generics:
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-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
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-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
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-- C_BASEADDR -- AXI4LITE slave: base address
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-- C_HIGHADDR -- AXI4LITE slave: high address
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--
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-- Definition of Ports:
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-- S_AXI_ACLK -- AXI4LITE slave: Clock
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-- S_AXI_ARESETN -- AXI4LITE slave: Reset
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-- S_AXI_AWADDR -- AXI4LITE slave: Write address
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-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
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-- S_AXI_WDATA -- AXI4LITE slave: Write data
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-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
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-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
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-- S_AXI_BREADY -- AXI4LITE slave: Response ready
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-- S_AXI_ARADDR -- AXI4LITE slave: Read address
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-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
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-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
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-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
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-- S_AXI_RDATA -- AXI4LITE slave: Read data
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-- S_AXI_RRESP -- AXI4LITE slave: Read data response
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-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
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-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
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-- S_AXI_BRESP -- AXI4LITE slave: Response
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-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
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-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
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------------------------------------------------------------------------------
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entity msec_ipcore_axilite is
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generic(
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-- Multiplier parameters
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C_NR_BITS_TOTAL : integer := 1536;
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C_NR_STAGES_TOTAL : integer := 96;
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C_NR_STAGES_LOW : integer := 32;
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C_SPLIT_PIPELINE : boolean := true;
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C_FIFO_DEPTH : integer := 32;
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C_MEM_STYLE : string := "xil_prim"; -- xil_prim, generic, asym are valid options
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C_FPGA_MAN : string := "xilinx"; -- xilinx, altera are valid options
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-- Bus protocol parameters
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C_S_AXI_DATA_WIDTH : integer := 32;
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C_S_AXI_ADDR_WIDTH : integer := 32;
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C_BASEADDR : std_logic_vector := X"FFFFFFFF";
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C_HIGHADDR : std_logic_vector := X"00000000"
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);
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port(
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--USER ports
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calc_time : out std_logic;
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IntrEvent : out std_logic;
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-------------------------
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-- AXI4lite interface
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-------------------------
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--- Global signals
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S_AXI_ACLK : in std_logic;
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S_AXI_ARESETN : in std_logic;
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--- Write address channel
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S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
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S_AXI_AWVALID : in std_logic;
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S_AXI_AWREADY : out std_logic;
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--- Write data channel
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S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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S_AXI_WVALID : in std_logic;
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S_AXI_WREADY : out std_logic;
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S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
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--- Write response channel
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S_AXI_BVALID : out std_logic;
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S_AXI_BREADY : in std_logic;
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S_AXI_BRESP : out std_logic_vector(1 downto 0);
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--- Read address channel
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S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
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S_AXI_ARVALID : in std_logic;
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S_AXI_ARREADY : out std_logic;
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--- Read data channel
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S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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S_AXI_RVALID : out std_logic;
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S_AXI_RREADY : in std_logic;
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S_AXI_RRESP : out std_logic_vector(1 downto 0)
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);
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attribute MAX_FANOUT : string;
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attribute SIGIS : string;
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attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
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attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
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attribute SIGIS of S_AXI_ACLK : signal is "Clk";
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attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
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end entity msec_ipcore_axilite;
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------------------------------------------------------------------------------
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-- Architecture section
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------------------------------------------------------------------------------
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architecture IMP of msec_ipcore_axilite is
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type axi_states is (addr_wait, read_state, write_state, response_state);
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signal state : axi_states;
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signal address : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
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signal reset : std_logic;
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signal S_AXI_BVALID_i : std_logic;
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-- selection signals
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signal cs_array : std_logic_vector(6 downto 0);
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signal slv_reg_selected : std_logic;
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signal op_mem_selected : std_logic;
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signal op_sel : std_logic_vector(1 downto 0);
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signal MNO_sel : std_logic;
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-- slave register signals
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signal slv_reg : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal slv_reg_write_enable : std_logic;
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signal load_flags : std_logic;
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-- core interface signeals
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signal write_enable : std_logic;
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signal core_write_enable : std_logic;
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signal core_fifo_push : std_logic;
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signal core_data_out : std_logic_vector(31 downto 0);
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signal core_rw_address : std_logic_vector(8 downto 0);
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------------------------------------------------------------------
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-- Signals for multiplier core interrupt
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------------------------------------------------------------------
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signal core_interrupt : std_logic;
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signal core_fifo_full : std_logic;
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signal core_fifo_nopush : std_logic;
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signal core_ready : std_logic;
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signal core_mem_collision : std_logic;
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------------------------------------------------------------------
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-- Signals for multiplier core control
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------------------------------------------------------------------
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signal core_start : std_logic;
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signal core_exp_m : std_logic;
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signal core_p_sel : std_logic_vector(1 downto 0);
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signal core_dest_op_single : std_logic_vector(1 downto 0);
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signal core_x_sel_single : std_logic_vector(1 downto 0);
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signal core_y_sel_single : std_logic_vector(1 downto 0);
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signal core_flags : std_logic_vector(15 downto 0);
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signal core_modulus_sel : std_logic;
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begin
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-- unused signals
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S_AXI_BRESP <= "00";
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S_AXI_RRESP <= "00";
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-- axi-lite slave state machine
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axi_slave_states : process (S_AXI_ACLK)
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begin
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if rising_edge(S_AXI_ACLK) then
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if S_AXI_ARESETN='0' then -- slave reset state
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S_AXI_RVALID <= '0';
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S_AXI_BVALID_i <= '0';
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S_AXI_ARREADY <= '0';
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S_AXI_WREADY <= '0';
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S_AXI_AWREADY <= '0';
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state <= addr_wait;
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address <= (others=>'0');
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write_enable <= '0';
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else
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case state is
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when addr_wait =>
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-- wait for a read or write address and latch it in
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if S_AXI_ARVALID = '1' then -- read
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state <= read_state;
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address <= S_AXI_ARADDR;
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S_AXI_ARREADY <= '1';
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elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then -- write
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state <= write_state;
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address <= S_AXI_AWADDR;
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else
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state <= addr_wait;
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end if;
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when read_state =>
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-- place correct data on bus and generate valid pulse
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S_AXI_ARREADY <= '0';
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S_AXI_RVALID <= '1';
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state <= response_state;
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when write_state =>
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-- generate a write pulse
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S_AXI_AWREADY <= '1';
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write_enable <= '1';
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S_AXI_WREADY <= '1';
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state <= response_state;
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when response_state =>
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write_enable <= '0';
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S_AXI_AWREADY <= '0';
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S_AXI_WREADY <= '0';
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S_AXI_BVALID_i <= '1';
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-- wait for response from master
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if (S_AXI_RREADY = '1') or (S_AXI_BVALID_i = '1' and S_AXI_BREADY = '1') then
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S_AXI_RVALID <= '0';
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S_AXI_BVALID_i <= '0';
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state <= addr_wait;
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else
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state <= response_state;
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end if;
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end case;
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end if;
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end if;
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end process;
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S_AXI_BVALID <= S_AXI_BVALID_i;
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-- place correct data on the read bus
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S_AXI_RDATA <= slv_reg when (slv_reg_selected='1') else
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core_data_out;
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-- SLAVE REG MAPPING
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-- core control signals
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core_p_sel <= slv_reg(31 downto 30);
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core_dest_op_single <= slv_reg(29 downto 28);
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core_x_sel_single <= slv_reg(27 downto 26);
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core_y_sel_single <= slv_reg(25 downto 24);
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core_start <= slv_reg(23);
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core_exp_m <= slv_reg(22);
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core_modulus_sel <= slv_reg(21);
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reset <= (not S_AXI_ARESETN) or slv_reg(20);
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-- implement slave register
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SLAVE_REG_WRITE_PROC : process( S_AXI_ACLK ) is
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begin
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if rising_edge(S_AXI_ACLK) then
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if S_AXI_ARESETN = '0' then
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slv_reg <= (others => '0');
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elsif load_flags = '1' then
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slv_reg <= slv_reg(31 downto 16) & core_flags;
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else
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if (slv_reg_write_enable='1') then
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slv_reg <= S_AXI_WDATA(31 downto 0);
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end if;
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end if;
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end if;
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end process SLAVE_REG_WRITE_PROC;
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-- interrupt and flags
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core_interrupt <= core_ready or core_mem_collision or core_fifo_full or core_fifo_nopush;
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IntrEvent <= core_interrupt;
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FLAGS_CNTRL_PROC : process(S_AXI_ACLK, S_AXI_ARESETN) is
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begin
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if S_AXI_ARESETN = '0' then
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core_flags <= (others => '0');
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load_flags <= '0';
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elsif rising_edge(S_AXI_ACLK) then
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if core_start = '1' then
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core_flags <= (others => '0');
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else
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if core_ready = '1' then
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core_flags(15) <= '1';
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else
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core_flags(15) <= core_flags(15);
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end if;
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if core_mem_collision = '1' then
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core_flags(14) <= '1';
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else
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core_flags(14) <= core_flags(14);
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end if;
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if core_fifo_full = '1' then
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core_flags(13) <= '1';
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else
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core_flags(13) <= core_flags(13);
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end if;
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if core_fifo_nopush = '1' then
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core_flags(12) <= '1';
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else
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core_flags(12) <= core_flags(12);
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end if;
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end if;
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load_flags <= core_interrupt;
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end if;
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end process FLAGS_CNTRL_PROC;
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-- adress decoder
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with address(14 downto 12) select
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cs_array <= "0000001" when "000", -- M
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"0000010" when "001", -- OP0
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"0000100" when "010", -- OP1
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"0001000" when "011", -- OP2
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"0010000" when "100", -- OP3
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"0100000" when "101", -- FIFO
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"1000000" when "110", -- user reg space
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"0000000" when others;
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slv_reg_selected <= cs_array(6);
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slv_reg_write_enable <= write_enable and slv_reg_selected;
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-- high if memory space is selected
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op_mem_selected <= cs_array(0) or cs_array(1) or cs_array(2) or cs_array(3) or cs_array(4);
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-- operand memory singals
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MNO_sel <= cs_array(0);
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with cs_array(4 downto 1) select
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op_sel <= "00" when "0001",
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"01" when "0010",
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"10" when "0100",
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"11" when "1000",
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"00" when others;
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core_rw_address <= MNO_sel & op_sel & address(7 downto 2);
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core_write_enable <= write_enable and op_mem_selected;
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-- FIFO signals
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core_fifo_push <= write_enable and cs_array(5);
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------------------------------------------
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-- Exponentiation core instance
|
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------------------------------------------
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msec: entity mod_sim_exp.mod_sim_exp_core
|
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generic map(
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C_NR_BITS_TOTAL => C_NR_BITS_TOTAL,
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C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
|
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C_NR_STAGES_LOW => C_NR_STAGES_LOW,
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C_SPLIT_PIPELINE => C_SPLIT_PIPELINE,
|
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C_FIFO_DEPTH => C_FIFO_DEPTH,
|
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C_MEM_STYLE => C_MEM_STYLE,
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C_FPGA_MAN => C_FPGA_MAN
|
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)
|
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port map(
|
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clk => S_AXI_ACLK,
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reset => reset,
|
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-- operand memory interface (plb shared memory)
|
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write_enable => core_write_enable,
|
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data_in => S_AXI_WDATA(31 downto 0),
|
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rw_address => core_rw_address,
|
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data_out => core_data_out,
|
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collision => core_mem_collision,
|
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-- op_sel fifo interface
|
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fifo_din => S_AXI_WDATA(31 downto 0),
|
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fifo_push => core_fifo_push,
|
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fifo_full => core_fifo_full,
|
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fifo_nopush => core_fifo_nopush,
|
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-- ctrl signals
|
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start => core_start,
|
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exp_m => core_exp_m,
|
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ready => core_ready,
|
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x_sel_single => core_x_sel_single,
|
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y_sel_single => core_y_sel_single,
|
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dest_op_single => core_dest_op_single,
|
|
p_sel => core_p_sel,
|
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calc_time => calc_time,
|
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modulus_sel => core_modulus_sel
|
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);
|
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|
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end IMP;
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