| Line 193... |
Line 193... |
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------------------------------------------------------------------
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------------------------------------------------------------------
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-- Signals for multiplier core control
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-- Signals for multiplier core control
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------------------------------------------------------------------
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------------------------------------------------------------------
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signal core_start : std_logic;
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signal core_start : std_logic;
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signal core_start_bit : std_logic;
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signal core_start_bit_d : std_logic;
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signal core_exp_m : std_logic;
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signal core_exp_m : std_logic;
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signal core_p_sel : std_logic_vector(1 downto 0);
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signal core_p_sel : std_logic_vector(1 downto 0);
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signal core_dest_op_single : std_logic_vector(1 downto 0);
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signal core_dest_op_single : std_logic_vector(1 downto 0);
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signal core_x_sel_single : std_logic_vector(1 downto 0);
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signal core_x_sel_single : std_logic_vector(1 downto 0);
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signal core_y_sel_single : std_logic_vector(1 downto 0);
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signal core_y_sel_single : std_logic_vector(1 downto 0);
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| Line 277... |
Line 279... |
-- core control signals
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-- core control signals
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core_p_sel <= slv_reg(31 downto 30);
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core_p_sel <= slv_reg(31 downto 30);
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core_dest_op_single <= slv_reg(29 downto 28);
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core_dest_op_single <= slv_reg(29 downto 28);
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core_x_sel_single <= slv_reg(27 downto 26);
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core_x_sel_single <= slv_reg(27 downto 26);
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core_y_sel_single <= slv_reg(25 downto 24);
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core_y_sel_single <= slv_reg(25 downto 24);
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core_start <= slv_reg(23);
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core_start_bit <= slv_reg(23);
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core_exp_m <= slv_reg(22);
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core_exp_m <= slv_reg(22);
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core_modulus_sel <= slv_reg(21);
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core_modulus_sel <= slv_reg(21);
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reset <= (not S_AXI_ARESETN) or slv_reg(20);
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reset <= (not S_AXI_ARESETN) or slv_reg(20);
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-- implement slave register
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-- implement slave register
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Line 300... |
end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process SLAVE_REG_WRITE_PROC;
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end process SLAVE_REG_WRITE_PROC;
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-- create start pulse of 1 clk wide
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START_PULSE : process(S_AXI_ACLK)
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begin
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if rising_edge(S_AXI_ACLK) then
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core_start_bit_d <= core_start_bit;
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end if;
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end process;
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core_start <= core_start_bit and not core_start_bit_d;
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-- interrupt and flags
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-- interrupt and flags
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core_interrupt <= core_ready or core_mem_collision or core_fifo_full or core_fifo_nopush;
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core_interrupt <= core_ready or core_mem_collision or core_fifo_full or core_fifo_nopush;
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IntrEvent <= core_interrupt;
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FLAGS_CNTRL_PROC : process(S_AXI_ACLK, reset) is
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FLAGS_CNTRL_PROC : process(S_AXI_ACLK, reset) is
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begin
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begin
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if reset = '1' then
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if reset = '1' then
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core_flags <= (others => '0');
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core_flags <= (others => '0');
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load_flags <= '0';
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load_flags <= '0';
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elsif rising_edge(S_AXI_ACLK) then
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elsif rising_edge(S_AXI_ACLK) then
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if core_start = '1' then
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if core_start = '1' then -- flags get resetted when core starts new operation
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core_flags <= (others => '0');
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core_flags <= (others => '0');
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else
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else
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if core_ready = '1' then
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if core_ready = '1' then
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core_flags(15) <= '1';
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core_flags(15) <= '1';
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else
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else
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Line 346... |
end if;
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end if;
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load_flags <= core_interrupt;
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load_flags <= core_interrupt;
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end if;
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end if;
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end process FLAGS_CNTRL_PROC;
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end process FLAGS_CNTRL_PROC;
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IntrEvent <= core_flags(15) or core_flags(14) or core_flags(13) or core_flags(12);
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-- adress decoder
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-- adress decoder
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with address(14 downto 12) select
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with address(14 downto 12) select
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cs_array <= "0000001" when "000", -- M
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cs_array <= "0000001" when "000", -- M
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"0000010" when "001", -- OP0
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"0000010" when "001", -- OP0
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"0000100" when "010", -- OP1
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"0000100" when "010", -- OP1
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