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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- mont_mult1536.vhd - entity/architecture pair
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-- mod_sim_exp_IPcore.vhd - entity/architecture pair
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- IMPORTANT:
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-- IMPORTANT:
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-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
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-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
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--
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--
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-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
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-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
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-- ** FOR A PARTICULAR PURPOSE. **
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-- ** FOR A PARTICULAR PURPOSE. **
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-- ** **
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-- ** **
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-- ***************************************************************************
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-- ***************************************************************************
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Filename: mont_mult1536.vhd
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-- Filename: mod_sim_exp_IPcore.vhd
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-- Version: 2.00.a
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-- Version: 0.20
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-- Description: Top level design, instantiates library components and user logic.
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-- Description: Top level design, instantiates library components and user logic.
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-- Date: Thu May 03 09:53:36 2012 (by Create and Import Peripheral Wizard)
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-- Date: Thu May 03 09:53:36 2012 (by Create and Import Peripheral Wizard)
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-- VHDL Standard: VHDL'93
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-- VHDL Standard: VHDL'93
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Naming Conventions:
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-- Naming Conventions:
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Line 161... |
C_NR_BITS_TOTAL : integer := 1536;
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C_NR_BITS_TOTAL : integer := 1536;
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C_NR_STAGES_TOTAL : integer := 96;
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C_NR_STAGES_TOTAL : integer := 96;
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C_NR_STAGES_LOW : integer := 32;
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C_NR_STAGES_LOW : integer := 32;
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C_SPLIT_PIPELINE : boolean := true;
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C_SPLIT_PIPELINE : boolean := true;
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C_FIFO_DEPTH : integer := 32;
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C_FIFO_DEPTH : integer := 32;
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C_MEM_STYLE : string := "xil_prim"; -- xil_prim, generic, asym are valid options
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C_DEVICE : string := "xilinx"; -- xilinx, altera are valid options
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-- ADD USER GENERICS ABOVE THIS LINE ---------------
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-- ADD USER GENERICS ABOVE THIS LINE ---------------
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-- DO NOT EDIT BELOW THIS LINE ---------------------
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-- DO NOT EDIT BELOW THIS LINE ---------------------
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-- Bus protocol parameters, do not add to or delete
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-- Bus protocol parameters, do not add to or delete
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C_BASEADDR : std_logic_vector := X"FFFFFFFF";
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C_BASEADDR : std_logic_vector := X"FFFFFFFF";
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Line 579... |
C_NR_BITS_TOTAL => C_NR_BITS_TOTAL,
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C_NR_BITS_TOTAL => C_NR_BITS_TOTAL,
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C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
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C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
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C_NR_STAGES_LOW => C_NR_STAGES_LOW,
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C_NR_STAGES_LOW => C_NR_STAGES_LOW,
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C_SPLIT_PIPELINE => C_SPLIT_PIPELINE,
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C_SPLIT_PIPELINE => C_SPLIT_PIPELINE,
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C_FIFO_DEPTH => C_FIFO_DEPTH,
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C_FIFO_DEPTH => C_FIFO_DEPTH,
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C_MEM_STYLE => C_MEM_STYLE,
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C_DEVICE => C_DEVICE,
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-- MAP USER GENERICS ABOVE THIS LINE ---------------
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-- MAP USER GENERICS ABOVE THIS LINE ---------------
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C_SLV_AWIDTH => USER_SLV_AWIDTH,
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C_SLV_AWIDTH => USER_SLV_AWIDTH,
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C_SLV_DWIDTH => USER_SLV_DWIDTH,
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C_SLV_DWIDTH => USER_SLV_DWIDTH,
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C_NUM_REG => USER_NUM_REG,
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C_NUM_REG => USER_NUM_REG,
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