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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] [plb/] [mod_sim_exp_IPcore.vhd] - Diff between revs 73 and 84

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Rev 73 Rev 84
Line 162... Line 162...
    C_NR_STAGES_TOTAL : integer := 96;
    C_NR_STAGES_TOTAL : integer := 96;
    C_NR_STAGES_LOW   : integer := 32;
    C_NR_STAGES_LOW   : integer := 32;
    C_SPLIT_PIPELINE  : boolean := true;
    C_SPLIT_PIPELINE  : boolean := true;
    C_FIFO_DEPTH      : integer := 32;
    C_FIFO_DEPTH      : integer := 32;
    C_MEM_STYLE       : string  := "xil_prim"; -- xil_prim, generic, asym are valid options
    C_MEM_STYLE       : string  := "xil_prim"; -- xil_prim, generic, asym are valid options
    C_DEVICE          : string  := "xilinx";    -- xilinx, altera are valid options
    C_FPGA_MAN        : string  := "xilinx";    -- xilinx, altera are valid options
    -- ADD USER GENERICS ABOVE THIS LINE ---------------
    -- ADD USER GENERICS ABOVE THIS LINE ---------------
 
 
    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- Bus protocol parameters, do not add to or delete
    -- Bus protocol parameters, do not add to or delete
    C_BASEADDR                     : std_logic_vector     := X"FFFFFFFF";
    C_BASEADDR                     : std_logic_vector     := X"FFFFFFFF";
Line 580... Line 580...
      C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
      C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
      C_NR_STAGES_LOW   => C_NR_STAGES_LOW,
      C_NR_STAGES_LOW   => C_NR_STAGES_LOW,
      C_SPLIT_PIPELINE  => C_SPLIT_PIPELINE,
      C_SPLIT_PIPELINE  => C_SPLIT_PIPELINE,
      C_FIFO_DEPTH      => C_FIFO_DEPTH,
      C_FIFO_DEPTH      => C_FIFO_DEPTH,
      C_MEM_STYLE       => C_MEM_STYLE,
      C_MEM_STYLE       => C_MEM_STYLE,
      C_DEVICE          => C_DEVICE,
      C_FPGA_MAN        => C_FPGA_MAN,
      -- MAP USER GENERICS ABOVE THIS LINE ---------------
      -- MAP USER GENERICS ABOVE THIS LINE ---------------
 
 
      C_SLV_AWIDTH                   => USER_SLV_AWIDTH,
      C_SLV_AWIDTH                   => USER_SLV_AWIDTH,
      C_SLV_DWIDTH                   => USER_SLV_DWIDTH,
      C_SLV_DWIDTH                   => USER_SLV_DWIDTH,
      C_NUM_REG                      => USER_NUM_REG,
      C_NUM_REG                      => USER_NUM_REG,

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