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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] [plb/] [mod_sim_exp_IPcore.vhd] - Diff between revs 84 and 94

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Rev 84 Rev 94
Line 160... Line 160...
    -- Multiplier parameters
    -- Multiplier parameters
    C_NR_BITS_TOTAL   : integer := 1536;
    C_NR_BITS_TOTAL   : integer := 1536;
    C_NR_STAGES_TOTAL : integer := 96;
    C_NR_STAGES_TOTAL : integer := 96;
    C_NR_STAGES_LOW   : integer := 32;
    C_NR_STAGES_LOW   : integer := 32;
    C_SPLIT_PIPELINE  : boolean := true;
    C_SPLIT_PIPELINE  : boolean := true;
    C_FIFO_DEPTH      : integer := 32;
    C_FIFO_AW         : integer := 7;
    C_MEM_STYLE       : string  := "xil_prim"; -- xil_prim, generic, asym are valid options
    C_MEM_STYLE       : string  := "xil_prim"; -- xil_prim, generic, asym are valid options
    C_FPGA_MAN        : string  := "xilinx";    -- xilinx, altera are valid options
    C_FPGA_MAN        : string  := "xilinx";    -- xilinx, altera are valid options
    -- ADD USER GENERICS ABOVE THIS LINE ---------------
    -- ADD USER GENERICS ABOVE THIS LINE ---------------
 
 
    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- DO NOT EDIT BELOW THIS LINE ---------------------
Line 199... Line 199...
  port
  port
  (
  (
    -- ADD USER PORTS BELOW THIS LINE ------------------
    -- ADD USER PORTS BELOW THIS LINE ------------------
    --USER ports added here
    --USER ports added here
   calc_time                      : out std_logic;
   calc_time                      : out std_logic;
 
    core_clk                       : in std_logic;
    -- ADD USER PORTS ABOVE THIS LINE ------------------
    -- ADD USER PORTS ABOVE THIS LINE ------------------
 
 
    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- Bus protocol ports, do not add to or delete
    -- Bus protocol ports, do not add to or delete
    SPLB_Clk                       : in  std_logic;
    SPLB_Clk                       : in  std_logic;
Line 578... Line 579...
      -- Multiplier parameters
      -- Multiplier parameters
      C_NR_BITS_TOTAL   => C_NR_BITS_TOTAL,
      C_NR_BITS_TOTAL   => C_NR_BITS_TOTAL,
      C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
      C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
      C_NR_STAGES_LOW   => C_NR_STAGES_LOW,
      C_NR_STAGES_LOW   => C_NR_STAGES_LOW,
      C_SPLIT_PIPELINE  => C_SPLIT_PIPELINE,
      C_SPLIT_PIPELINE  => C_SPLIT_PIPELINE,
      C_FIFO_DEPTH      => C_FIFO_DEPTH,
      C_FIFO_AW         => C_FIFO_AW,
      C_MEM_STYLE       => C_MEM_STYLE,
      C_MEM_STYLE       => C_MEM_STYLE,
      C_FPGA_MAN        => C_FPGA_MAN,
      C_FPGA_MAN        => C_FPGA_MAN,
      -- MAP USER GENERICS ABOVE THIS LINE ---------------
      -- MAP USER GENERICS ABOVE THIS LINE ---------------
 
 
      C_SLV_AWIDTH                   => USER_SLV_AWIDTH,
      C_SLV_AWIDTH                   => USER_SLV_AWIDTH,
Line 594... Line 595...
    port map
    port map
    (
    (
      -- MAP USER PORTS BELOW THIS LINE ------------------
      -- MAP USER PORTS BELOW THIS LINE ------------------
      --USER ports mapped here
      --USER ports mapped here
      calc_time                      => calc_time,
      calc_time                      => calc_time,
 
      core_clk                       => core_clk,
      -- MAP USER PORTS ABOVE THIS LINE ------------------
      -- MAP USER PORTS ABOVE THIS LINE ------------------
 
 
      Bus2IP_Clk                     => ipif_Bus2IP_Clk,
      Bus2IP_Clk                     => ipif_Bus2IP_Clk,
      Bus2IP_Reset                   => rst_Bus2IP_Reset,
      Bus2IP_Reset                   => rst_Bus2IP_Reset,
      Bus2IP_Addr                    => ipif_Bus2IP_Addr,
      Bus2IP_Addr                    => ipif_Bus2IP_Addr,

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