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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] [plb/] [user_logic.vhd] - Diff between revs 43 and 45

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Rev 43 Rev 45
Line 175... Line 175...
 
 
  ------------------------------------------------------------------
  ------------------------------------------------------------------
  -- Signals for multiplier core control
  -- Signals for multiplier core control
  ------------------------------------------------------------------
  ------------------------------------------------------------------
  signal core_start                     : std_logic;
  signal core_start                     : std_logic;
  signal core_run_auto                  : std_logic;
  signal core_exp_m                     : std_logic;
  signal core_p_sel                     : std_logic_vector(1 downto 0);
  signal core_p_sel                     : std_logic_vector(1 downto 0);
  signal core_dest_op_single            : std_logic_vector(1 downto 0);
  signal core_dest_op_single            : std_logic_vector(1 downto 0);
  signal core_x_sel_single              : std_logic_vector(1 downto 0);
  signal core_x_sel_single              : std_logic_vector(1 downto 0);
  signal core_y_sel_single              : std_logic_vector(1 downto 0);
  signal core_y_sel_single              : std_logic_vector(1 downto 0);
  signal core_flags                     : std_logic_vector(15 downto 0);
  signal core_flags                     : std_logic_vector(15 downto 0);
Line 383... Line 383...
 
 
  ------------------------------------------
  ------------------------------------------
  -- Map slv_reg0 bits to core control signals 
  -- Map slv_reg0 bits to core control signals 
  ------------------------------------------
  ------------------------------------------
  core_start <= slv_reg0(8);
  core_start <= slv_reg0(8);
  core_run_auto <= slv_reg0(9);
  core_exp_m <= slv_reg0(9);
  core_p_sel <= slv_reg0(0 to 1);
  core_p_sel <= slv_reg0(0 to 1);
  core_dest_op_single <= slv_reg0(2 to 3);
  core_dest_op_single <= slv_reg0(2 to 3);
  core_x_sel_single <= slv_reg0(4 to 5);
  core_x_sel_single <= slv_reg0(4 to 5);
  core_y_sel_single <= slv_reg0(6 to 7);
  core_y_sel_single <= slv_reg0(6 to 7);
 
 
Line 415... Line 415...
    fifo_push   => core_fifo_push,
    fifo_push   => core_fifo_push,
    fifo_full   => core_fifo_full,
    fifo_full   => core_fifo_full,
    fifo_nopush => core_fifo_nopush,
    fifo_nopush => core_fifo_nopush,
      -- ctrl signals
      -- ctrl signals
    start          => core_start,
    start          => core_start,
    run_auto       => core_run_auto,
    exp_m          => core_exp_m,
    ready          => core_ready,
    ready          => core_ready,
    x_sel_single   => core_x_sel_single,
    x_sel_single   => core_x_sel_single,
    y_sel_single   => core_y_sel_single,
    y_sel_single   => core_y_sel_single,
    dest_op_single => core_dest_op_single,
    dest_op_single => core_dest_op_single,
    p_sel          => core_p_sel,
    p_sel          => core_p_sel,

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