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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] [plb/] [user_logic.vhd] - Diff between revs 84 and 94

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Rev 84 Rev 94
Line 98... Line 98...
    -- Multiplier parameters
    -- Multiplier parameters
    C_NR_BITS_TOTAL   : integer := 1536;
    C_NR_BITS_TOTAL   : integer := 1536;
    C_NR_STAGES_TOTAL : integer := 96;
    C_NR_STAGES_TOTAL : integer := 96;
    C_NR_STAGES_LOW   : integer := 32;
    C_NR_STAGES_LOW   : integer := 32;
    C_SPLIT_PIPELINE  : boolean := true;
    C_SPLIT_PIPELINE  : boolean := true;
    C_FIFO_DEPTH      : integer := 32;
    C_FIFO_AW         : integer := 7;
    C_MEM_STYLE       : string  := "xil_prim"; -- xil_prim, generic, asym are valid options
    C_MEM_STYLE       : string  := "xil_prim"; -- xil_prim, generic, asym are valid options
    C_FPGA_MAN        : string  := "xilinx";    -- xilinx, altera are valid options
    C_FPGA_MAN        : string  := "xilinx";    -- xilinx, altera are valid options
    -- ADD USER GENERICS ABOVE THIS LINE ---------------
    -- ADD USER GENERICS ABOVE THIS LINE ---------------
 
 
    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- DO NOT EDIT BELOW THIS LINE ---------------------
Line 117... Line 117...
  port
  port
  (
  (
    -- ADD USER PORTS BELOW THIS LINE ------------------
    -- ADD USER PORTS BELOW THIS LINE ------------------
    --USER ports added here
    --USER ports added here
         calc_time                      : out std_logic;
         calc_time                      : out std_logic;
        -- ctrl_sigs                      : out std_logic_vector( downto );
          core_clk                       : in std_logic;
    -- ADD USER PORTS ABOVE THIS LINE ------------------
    -- ADD USER PORTS ABOVE THIS LINE ------------------
 
 
    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- Bus protocol ports, do not add to or delete
    -- Bus protocol ports, do not add to or delete
    Bus2IP_Clk                     : in  std_logic;
    Bus2IP_Clk                     : in  std_logic;
Line 404... Line 404...
  generic map(
  generic map(
    C_NR_BITS_TOTAL   => C_NR_BITS_TOTAL,
    C_NR_BITS_TOTAL   => C_NR_BITS_TOTAL,
    C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
    C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
    C_NR_STAGES_LOW   => C_NR_STAGES_LOW,
    C_NR_STAGES_LOW   => C_NR_STAGES_LOW,
    C_SPLIT_PIPELINE  => C_SPLIT_PIPELINE,
    C_SPLIT_PIPELINE  => C_SPLIT_PIPELINE,
    C_FIFO_DEPTH      => C_FIFO_DEPTH,
    C_FIFO_AW         => C_FIFO_AW,
    C_MEM_STYLE       => C_MEM_STYLE,
    C_MEM_STYLE       => C_MEM_STYLE,
    C_FPGA_MAN        => C_FPGA_MAN
    C_FPGA_MAN        => C_FPGA_MAN
  )
  )
  port map(
  port map(
    clk   => Bus2IP_Clk,
    core_clk  => core_clk,
 
    bus_clk   => Bus2IP_Clk,
    reset => Bus2IP_Reset,
    reset => Bus2IP_Reset,
      -- operand memory interface (plb shared memory)
      -- operand memory interface (plb shared memory)
    write_enable => core_write_enable,
    write_enable => core_write_enable,
    data_in      => core_data_in,
    data_in      => core_data_in,
    rw_address   => core_rw_address,
    rw_address   => core_rw_address,

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