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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [ram/] [dpram_generic.vhd] - Diff between revs 59 and 60

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Line 4... Line 4...
----  This file is part of the                                    ----
----  This file is part of the                                    ----
----    Modular Simultaneous Exponentiation Core project          ---- 
----    Modular Simultaneous Exponentiation Core project          ---- 
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
----                                                              ---- 
----                                                              ---- 
----  Description                                                 ---- 
----  Description                                                 ---- 
----    behovorial description of a dual port ram with one 32-bit ----
----    behavorial description of a dual port ram with one 32-bit ----
----    write port and one 32-bit read port                       ----            
----    write port and one 32-bit read port                       ----            
----                                                              ---- 
----                                                              ---- 
----  Dependencies: none                                          ----
----  Dependencies: none                                          ----
----                                                              ----
----                                                              ----
----  Authors:                                                    ----
----  Authors:                                                    ----
Line 73... Line 73...
  signal ram : ram_type;
  signal ram : ram_type;
 
 
  -- xilinx constraint to use blockram resources
  -- xilinx constraint to use blockram resources
  attribute ram_style : string;
  attribute ram_style : string;
  attribute ram_style of ram:signal is "block";
  attribute ram_style of ram:signal is "block";
  -- altera constraint
  -- altera constraints:
  attribute ramstyle : string;
  -- for smal depths:
  attribute ramstyle of ram : signal is "M9K, no_rw_check";
  --  if the synthesis option : allow any size of RAM to be inferred, is on these lines 
 
  --  may be left uncommented.
 
  --  uncomment this attribute if that option is of and you know wich primitives should be used.
 
  --attribute ramstyle : string;
 
  --attribute ramstyle of ram : signal is "M9K, no_rw_check";
begin
begin
  process (clk)
  process (clk)
  begin
  begin
    if (clk'event and clk = '1') then
    if (clk'event and clk = '1') then
      if (we = '1') then
      if (we = '1') then

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