OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [ram/] [dpramblock_asym.vhd] - Diff between revs 90 and 94

Show entire file | Details | Blame | View Log

Rev 90 Rev 94
Line 60... Line 60...
    width  : integer := 256;  -- read width
    width  : integer := 256;  -- read width
    depth  : integer := 2;    -- nr of (width)-bit words
    depth  : integer := 2;    -- nr of (width)-bit words
    device : string  := "xilinx"
    device : string  := "xilinx"
  );
  );
  port (
  port (
    clk : in std_logic;
    -- write port A
    -- write port
    clkA   : in std_logic;
    waddr : in std_logic_vector(log2((width*depth)/32)-1 downto 0);
    waddrA : in std_logic_vector(log2((width*depth)/32)-1 downto 0);
    we    : in std_logic;
    weA    : in std_logic;
    din   : in std_logic_vector(31 downto 0);
    dinA   : in std_logic_vector(31 downto 0);
    -- read port
    -- read port B
    raddr : in std_logic_vector(log2(depth)-1 downto 0);
    clkB   : in std_logic;
    dout  : out std_logic_vector(width-1 downto 0)
    raddrB : in std_logic_vector(log2(depth)-1 downto 0);
 
    doutB  : out std_logic_vector(width-1 downto 0)
  );
  );
end dpramblock_asym;
end dpramblock_asym;
 
 
architecture structural of dpramblock_asym is
architecture structural of dpramblock_asym is
  -- constants
  -- constants
Line 90... Line 91...
      rddepth => depth,
      rddepth => depth,
      wrwidth => RAMwrwidth,
      wrwidth => RAMwrwidth,
      device  => device
      device  => device
    )
    )
    port map(
    port map(
      clk => clk,
 
      -- write port
      -- write port
      waddr => waddr,
      clkA   => clkA,
      we    => we,
      waddrA => waddrA,
      din   => din((i+1)*RAMwrwidth-1 downto RAMwrwidth*i),
      weA    => weA,
 
      dinA   => dinA((i+1)*RAMwrwidth-1 downto RAMwrwidth*i),
      -- read port
      -- read port
      raddr => raddr,
      clkB   => clkB,
      dout  => dout_RAM(i)
      raddrB => raddrB,
 
      doutB  => dout_RAM(i)
    );
    );
 
 
    map_output : for j in 0 to nrRAMs-1 generate
    map_output : for j in 0 to nrRAMs-1 generate
      dout(j*32+(i+1)*RAMwrwidth-1 downto j*32+i*RAMwrwidth)
      doutB(j*32+(i+1)*RAMwrwidth-1 downto j*32+i*RAMwrwidth)
          <= dout_RAM(i)((j+1)*RAMwrwidth-1 downto j*RAMwrwidth);
          <= dout_RAM(i)((j+1)*RAMwrwidth-1 downto j*RAMwrwidth);
    end generate;
    end generate;
  end generate;
  end generate;
end structural;
end structural;
 
 
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.