OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [ram/] [tdpram_generic.vhd] - Diff between revs 59 and 60

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 59 Rev 60
Line 1... Line 1...
----------------------------------------------------------------------  
----------------------------------------------------------------------  
----  dpram_generic                                               ---- 
----  tdpram_generic                                              ---- 
----                                                              ---- 
----                                                              ---- 
----  This file is part of the                                    ----
----  This file is part of the                                    ----
----    Modular Simultaneous Exponentiation Core project          ---- 
----    Modular Simultaneous Exponentiation Core project          ---- 
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
----                                                              ---- 
----                                                              ---- 
----  Description                                                 ---- 
----  Description                                                 ---- 
----    behovorial description of a dual port ram with one 32-bit ----
----    behavorial description of a true dual port ram with 2     ----
----    write port and one 32-bit read port                       ----            
----    32-bit write/read ports                                   ----        
----                                                              ---- 
----                                                              ---- 
----  Dependencies: none                                          ----
----  Dependencies: none                                          ----
----                                                              ----
----                                                              ----
----  Authors:                                                    ----
----  Authors:                                                    ----
----      - Geoffrey Ottoy, DraMCo research group                 ----
----      - Geoffrey Ottoy, DraMCo research group                 ----
Line 77... Line 77...
  shared variable RAM: ram_type;
  shared variable RAM: ram_type;
 
 
  -- xilinx constraint to use blockram resources
  -- xilinx constraint to use blockram resources
  attribute ram_style : string;
  attribute ram_style : string;
  attribute ram_style of RAM:variable is "block";
  attribute ram_style of RAM:variable is "block";
  -- altera constraint
  -- altera constraints:
 
  -- for smal depths:
 
  --  if the synthesis option : allow any size of RAM to be inferred, is on these lines 
 
  --  may be left uncommented.
 
  --  uncomment this attribute if that option is of and you know wich primitives should be used.
  --attribute ramstyle : string;
  --attribute ramstyle : string;
  --attribute ramstyle of RAM:variable is "M9K, no_rw_check";
  --attribute ramstyle of ram : signal is "M9K, no_rw_check";
begin
begin
  -- port A
  -- port A
  process (clkA)
  process (clkA)
  begin
  begin
    if (clkA'event and clkA = '1') then
    if (clkA'event and clkA = '1') then

powered by: WebSVN 2.1.0

© copyright 1999-2023 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.