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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [ram/] [tdpramblock_asym.vhd] - Diff between revs 90 and 94

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Rev 90 Rev 94
Line 60... Line 60...
    depth  : integer := 4;    -- nr of (width)-bit words
    depth  : integer := 4;    -- nr of (width)-bit words
    width  : integer := 512;  -- width of portB
    width  : integer := 512;  -- width of portB
    device : string  := "xilinx"
    device : string  := "xilinx"
  );
  );
  port  (
  port  (
    clk : in std_logic;
 
    -- port A 32-bit
    -- port A 32-bit
 
    clkA  : in std_logic;
    addrA : in std_logic_vector(log2((width*depth)/32)-1 downto 0);
    addrA : in std_logic_vector(log2((width*depth)/32)-1 downto 0);
    weA   : in std_logic;
    weA   : in std_logic;
    dinA  : in std_logic_vector(31 downto 0);
    dinA  : in std_logic_vector(31 downto 0);
    doutA : out std_logic_vector(31 downto 0);
    doutA : out std_logic_vector(31 downto 0);
    -- port B (width)-bit
    -- port B (width)-bit
 
    clkB  : in std_logic;
    addrB : in std_logic_vector(log2(depth)-1 downto 0);
    addrB : in std_logic_vector(log2(depth)-1 downto 0);
    weB   : in std_logic;
    weB   : in std_logic;
    dinB  : in std_logic_vector(width-1 downto 0);
    dinB  : in std_logic_vector(width-1 downto 0);
    doutB : out std_logic_vector(width-1 downto 0)
    doutB : out std_logic_vector(width-1 downto 0)
  );
  );
Line 93... Line 94...
      widthA => RAMwidthA,
      widthA => RAMwidthA,
      depthB => depth,
      depthB => depth,
      device => device
      device => device
    )
    )
    port map(
    port map(
      clk => clk,
 
      -- port A (widthA)-bit
      -- port A (widthA)-bit
 
      clkA  => clkA,
      addrA => addrA,
      addrA => addrA,
      weA   => weA,
      weA   => weA,
      dinA  => dinA((i+1)*RAMwidthA-1 downto RAMwidthA*i),
      dinA  => dinA((i+1)*RAMwidthA-1 downto RAMwidthA*i),
      doutA => doutA((i+1)*RAMwidthA-1 downto RAMwidthA*i),
      doutA => doutA((i+1)*RAMwidthA-1 downto RAMwidthA*i),
      -- port B 32-bit
      -- port B 32-bit
 
      clkB  => clkB,
      addrB => addrB,
      addrB => addrB,
      weB   => weB,
      weB   => weB,
      dinB  => dinB_RAM(i),
      dinB  => dinB_RAM(i),
      doutB => doutB_RAM(i)
      doutB => doutB_RAM(i)
    );
    );

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