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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [sim/] [Makefile] - Diff between revs 65 and 70

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Rev 65 Rev 70
Line 1... Line 1...
#VCOM    = /usr/local/bin/vcom
#VCOM    = /usr/local/bin/vcom
VCOMOPS = -explicit -check_synthesis -2002 -quiet
VCOMOPS = -explicit -check_synthesis -2002 -quiet
VLOGOPS = -vopt -nocovercells
 
#MAKEFLAGS = --silent
#MAKEFLAGS = --silent
HDL_DIR = ../rtl/vhdl/
HDL_DIR = ../rtl/vhdl/
VER_DIR = ../rtl/verilog/
 
 
 
 
 
##
##
# avs_aes hdl files
# avs_aes hdl files
##
##
CORE_SRC =$(HDL_DIR)/core/std_functions.vhd \
CORE_SRC =$(HDL_DIR)/core/std_functions.vhd \
                 $(HDL_DIR)/core/mod_sim_exp_pkg.vhd \
                 $(HDL_DIR)/core/mod_sim_exp_pkg.vhd \
                 $(HDL_DIR)/ram/dpram_generic.vhd \
                 $(HDL_DIR)/ram/dpram_generic.vhd \
                 $(HDL_DIR)/ram/tdpram_generic.vhd \
                 $(HDL_DIR)/ram/tdpram_generic.vhd \
 
                 $(HDL_DIR)/ram/dpram_asym.vhd \
 
                 $(HDL_DIR)/ram/dpramblock_asym.vhd \
 
                 $(HDL_DIR)/core/modulus_ram_asym.vhd \
 
                 $(HDL_DIR)/ram/tdpram_asym.vhd \
 
                 $(HDL_DIR)/ram/tdpramblock_asym.vhd \
 
                 $(HDL_DIR)/core/operand_ram_asym.vhd \
                 $(HDL_DIR)/core/fifo_generic.vhd \
                 $(HDL_DIR)/core/fifo_generic.vhd \
                 $(HDL_DIR)/core/modulus_ram_gen.vhd \
                 $(HDL_DIR)/core/modulus_ram_gen.vhd \
                 $(HDL_DIR)/core/operand_ram_gen.vhd \
                 $(HDL_DIR)/core/operand_ram_gen.vhd \
                 $(HDL_DIR)/core/adder_block.vhd \
                 $(HDL_DIR)/core/adder_block.vhd \
                 $(HDL_DIR)/core/autorun_cntrl.vhd \
                 $(HDL_DIR)/core/autorun_cntrl.vhd \
Line 40... Line 43...
                 $(HDL_DIR)/core/sys_last_cell_logic.vhd \
                 $(HDL_DIR)/core/sys_last_cell_logic.vhd \
                 $(HDL_DIR)/core/sys_first_cell_logic.vhd \
                 $(HDL_DIR)/core/sys_first_cell_logic.vhd \
                 $(HDL_DIR)/core/sys_pipeline.vhd \
                 $(HDL_DIR)/core/sys_pipeline.vhd \
                 $(HDL_DIR)/core/mont_multiplier.vhd \
                 $(HDL_DIR)/core/mont_multiplier.vhd \
 
 
VER_SRC =$(VER_DIR)generic_spram.v \
 
                $(VER_DIR)generic_dpram.v \
 
                $(VER_DIR)generic_tpram.v \
 
                $(VER_DIR)generic_fifo_sc_a.v \
 
                $(VER_DIR)generic_fifo_sc_b.v \
 
 
 
##
##
# Testbench HDL file
# Testbench HDL file
##
##
TB_SRC_DIR = ../bench/vhdl/
TB_SRC_DIR = ../bench/vhdl/
Line 70... Line 68...
 
 
mod_sim_exp_com: mod_sim_exp_lib
mod_sim_exp_com: mod_sim_exp_lib
        #echo --
        #echo --
        #echo building Modular Exponentiation Core
        #echo building Modular Exponentiation Core
        #echo --
        #echo --
        #vlog $(VLOGOPS) -work mod_sim_exp $(VER_SRC)
 
        vcom $(VCOMOPS) -work mod_sim_exp $(CORE_SRC)
        vcom $(VCOMOPS) -work mod_sim_exp $(CORE_SRC)
        #echo Done!
        #echo Done!
 
 
mod_sim_exp_tb: work_lib
mod_sim_exp_tb: work_lib
        #echo --
        #echo --

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