OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [sim/] [Makefile] - Diff between revs 65 and 70

Go to most recent revision | Only display areas with differences | Details | Blame | View Log

Rev 65 Rev 70
#VCOM    = /usr/local/bin/vcom
#VCOM    = /usr/local/bin/vcom
VCOMOPS = -explicit -check_synthesis -2002 -quiet
VCOMOPS = -explicit -check_synthesis -2002 -quiet
VLOGOPS = -vopt -nocovercells
 
#MAKEFLAGS = --silent
#MAKEFLAGS = --silent
HDL_DIR = ../rtl/vhdl/
HDL_DIR = ../rtl/vhdl/
VER_DIR = ../rtl/verilog/
 
 
 
 
 
##
##
# avs_aes hdl files
# avs_aes hdl files
##
##
CORE_SRC =$(HDL_DIR)/core/std_functions.vhd \
CORE_SRC =$(HDL_DIR)/core/std_functions.vhd \
                 $(HDL_DIR)/core/mod_sim_exp_pkg.vhd \
                 $(HDL_DIR)/core/mod_sim_exp_pkg.vhd \
                 $(HDL_DIR)/ram/dpram_generic.vhd \
                 $(HDL_DIR)/ram/dpram_generic.vhd \
                 $(HDL_DIR)/ram/tdpram_generic.vhd \
                 $(HDL_DIR)/ram/tdpram_generic.vhd \
 
                 $(HDL_DIR)/ram/dpram_asym.vhd \
 
                 $(HDL_DIR)/ram/dpramblock_asym.vhd \
 
                 $(HDL_DIR)/core/modulus_ram_asym.vhd \
 
                 $(HDL_DIR)/ram/tdpram_asym.vhd \
 
                 $(HDL_DIR)/ram/tdpramblock_asym.vhd \
 
                 $(HDL_DIR)/core/operand_ram_asym.vhd \
                 $(HDL_DIR)/core/fifo_generic.vhd \
                 $(HDL_DIR)/core/fifo_generic.vhd \
                 $(HDL_DIR)/core/modulus_ram_gen.vhd \
                 $(HDL_DIR)/core/modulus_ram_gen.vhd \
                 $(HDL_DIR)/core/operand_ram_gen.vhd \
                 $(HDL_DIR)/core/operand_ram_gen.vhd \
                 $(HDL_DIR)/core/adder_block.vhd \
                 $(HDL_DIR)/core/adder_block.vhd \
                 $(HDL_DIR)/core/autorun_cntrl.vhd \
                 $(HDL_DIR)/core/autorun_cntrl.vhd \
                 $(HDL_DIR)/core/cell_1b_adder.vhd \
                 $(HDL_DIR)/core/cell_1b_adder.vhd \
                 $(HDL_DIR)/core/cell_1b_mux.vhd \
                 $(HDL_DIR)/core/cell_1b_mux.vhd \
                 $(HDL_DIR)/core/cell_1b.vhd \
                 $(HDL_DIR)/core/cell_1b.vhd \
                 $(HDL_DIR)/core/counter_sync.vhd \
                 $(HDL_DIR)/core/counter_sync.vhd \
                 $(HDL_DIR)/core/d_flip_flop.vhd \
                 $(HDL_DIR)/core/d_flip_flop.vhd \
                 $(HDL_DIR)/core/fifo_primitive.vhd \
                 $(HDL_DIR)/core/fifo_primitive.vhd \
                 $(HDL_DIR)/core/modulus_ram.vhd \
                 $(HDL_DIR)/core/modulus_ram.vhd \
                 $(HDL_DIR)/core/mont_ctrl.vhd \
                 $(HDL_DIR)/core/mont_ctrl.vhd \
                 $(HDL_DIR)/core/mod_sim_exp_core.vhd \
                 $(HDL_DIR)/core/mod_sim_exp_core.vhd \
                 $(HDL_DIR)/core/operand_dp.vhd \
                 $(HDL_DIR)/core/operand_dp.vhd \
                 $(HDL_DIR)/core/operand_mem.vhd \
                 $(HDL_DIR)/core/operand_mem.vhd \
                 $(HDL_DIR)/core/operand_ram.vhd \
                 $(HDL_DIR)/core/operand_ram.vhd \
                 $(HDL_DIR)/core/operands_sp.vhd \
                 $(HDL_DIR)/core/operands_sp.vhd \
                 $(HDL_DIR)/core/register_1b.vhd \
                 $(HDL_DIR)/core/register_1b.vhd \
                 $(HDL_DIR)/core/register_n.vhd \
                 $(HDL_DIR)/core/register_n.vhd \
                 $(HDL_DIR)/core/standard_cell_block.vhd \
                 $(HDL_DIR)/core/standard_cell_block.vhd \
                 $(HDL_DIR)/core/stepping_logic.vhd \
                 $(HDL_DIR)/core/stepping_logic.vhd \
                 $(HDL_DIR)/core/x_shift_reg.vhd \
                 $(HDL_DIR)/core/x_shift_reg.vhd \
                 $(HDL_DIR)/core/sys_stage.vhd \
                 $(HDL_DIR)/core/sys_stage.vhd \
                 $(HDL_DIR)/core/sys_last_cell_logic.vhd \
                 $(HDL_DIR)/core/sys_last_cell_logic.vhd \
                 $(HDL_DIR)/core/sys_first_cell_logic.vhd \
                 $(HDL_DIR)/core/sys_first_cell_logic.vhd \
                 $(HDL_DIR)/core/sys_pipeline.vhd \
                 $(HDL_DIR)/core/sys_pipeline.vhd \
                 $(HDL_DIR)/core/mont_multiplier.vhd \
                 $(HDL_DIR)/core/mont_multiplier.vhd \
 
 
VER_SRC =$(VER_DIR)generic_spram.v \
 
                $(VER_DIR)generic_dpram.v \
 
                $(VER_DIR)generic_tpram.v \
 
                $(VER_DIR)generic_fifo_sc_a.v \
 
                $(VER_DIR)generic_fifo_sc_b.v \
 
 
 
##
##
# Testbench HDL file
# Testbench HDL file
##
##
TB_SRC_DIR = ../bench/vhdl/
TB_SRC_DIR = ../bench/vhdl/
TB_SRC =  $(TB_SRC_DIR)mod_sim_exp_core_tb.vhd
TB_SRC =  $(TB_SRC_DIR)mod_sim_exp_core_tb.vhd
#######################################
#######################################
all: mod_sim_exp
all: mod_sim_exp
clean:
clean:
        rm -rf *_lib
        rm -rf *_lib
mod_sim_exp_lib:
mod_sim_exp_lib:
        vlib mod_sim_exp
        vlib mod_sim_exp
work_lib:
work_lib:
        vlib work
        vlib work
libs: mod_sim_exp work_lib
libs: mod_sim_exp work_lib
mod_sim_exp_com: mod_sim_exp_lib
mod_sim_exp_com: mod_sim_exp_lib
        #echo --
        #echo --
        #echo building Modular Exponentiation Core
        #echo building Modular Exponentiation Core
        #echo --
        #echo --
        #vlog $(VLOGOPS) -work mod_sim_exp $(VER_SRC)
 
        vcom $(VCOMOPS) -work mod_sim_exp $(CORE_SRC)
        vcom $(VCOMOPS) -work mod_sim_exp $(CORE_SRC)
        #echo Done!
        #echo Done!
mod_sim_exp_tb: work_lib
mod_sim_exp_tb: work_lib
        #echo --
        #echo --
        #echo building Modular Exponentiation Core Testbench
        #echo building Modular Exponentiation Core Testbench
        #echo --
        #echo --
        vcom $(VCOMOPS) -work work $(TB_SRC)
        vcom $(VCOMOPS) -work work $(TB_SRC)
mod_sim_exp: mod_sim_exp_com mod_sim_exp_tb
mod_sim_exp: mod_sim_exp_com mod_sim_exp_tb
        vsim -c -do mod_sim_exp.do -lib work mod_sim_exp_core_tb
        vsim -c -do mod_sim_exp.do -lib work mod_sim_exp_core_tb
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.