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[/] [mod_sim_exp/] [trunk/] [sim/] [Makefile] - Diff between revs 70 and 84

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Rev 70 Rev 84
Line 4... Line 4...
HDL_DIR = ../rtl/vhdl/
HDL_DIR = ../rtl/vhdl/
 
 
##
##
# avs_aes hdl files
# avs_aes hdl files
##
##
CORE_SRC =$(HDL_DIR)/core/std_functions.vhd \
CORE_SRC =$(HDL_DIR)core/std_functions.vhd \
                 $(HDL_DIR)/core/mod_sim_exp_pkg.vhd \
                 $(HDL_DIR)core/mod_sim_exp_pkg.vhd \
                 $(HDL_DIR)/ram/dpram_generic.vhd \
                 $(HDL_DIR)ram/dpram_generic.vhd \
                 $(HDL_DIR)/ram/tdpram_generic.vhd \
                 $(HDL_DIR)ram/tdpram_generic.vhd \
                 $(HDL_DIR)/ram/dpram_asym.vhd \
                 $(HDL_DIR)ram/dpram_asym.vhd \
                 $(HDL_DIR)/ram/dpramblock_asym.vhd \
                 $(HDL_DIR)ram/dpramblock_asym.vhd \
                 $(HDL_DIR)/core/modulus_ram_asym.vhd \
                 $(HDL_DIR)core/modulus_ram_asym.vhd \
                 $(HDL_DIR)/ram/tdpram_asym.vhd \
                 $(HDL_DIR)ram/tdpram_asym.vhd \
                 $(HDL_DIR)/ram/tdpramblock_asym.vhd \
                 $(HDL_DIR)ram/tdpramblock_asym.vhd \
                 $(HDL_DIR)/core/operand_ram_asym.vhd \
                 $(HDL_DIR)core/operand_ram_asym.vhd \
                 $(HDL_DIR)/core/fifo_generic.vhd \
                 $(HDL_DIR)core/fifo_generic.vhd \
                 $(HDL_DIR)/core/modulus_ram_gen.vhd \
                 $(HDL_DIR)core/modulus_ram_gen.vhd \
                 $(HDL_DIR)/core/operand_ram_gen.vhd \
                 $(HDL_DIR)core/operand_ram_gen.vhd \
                 $(HDL_DIR)/core/adder_block.vhd \
                 $(HDL_DIR)core/adder_block.vhd \
                 $(HDL_DIR)/core/autorun_cntrl.vhd \
                 $(HDL_DIR)core/autorun_cntrl.vhd \
                 $(HDL_DIR)/core/cell_1b_adder.vhd \
                 $(HDL_DIR)core/cell_1b_adder.vhd \
                 $(HDL_DIR)/core/cell_1b_mux.vhd \
                 $(HDL_DIR)core/cell_1b_mux.vhd \
                 $(HDL_DIR)/core/cell_1b.vhd \
                 $(HDL_DIR)core/cell_1b.vhd \
                 $(HDL_DIR)/core/counter_sync.vhd \
                 $(HDL_DIR)core/counter_sync.vhd \
                 $(HDL_DIR)/core/d_flip_flop.vhd \
                 $(HDL_DIR)core/d_flip_flop.vhd \
                 $(HDL_DIR)/core/fifo_primitive.vhd \
                 $(HDL_DIR)core/fifo_primitive.vhd \
                 $(HDL_DIR)/core/modulus_ram.vhd \
                 $(HDL_DIR)core/modulus_ram.vhd \
                 $(HDL_DIR)/core/mont_ctrl.vhd \
                 $(HDL_DIR)core/mont_ctrl.vhd \
                 $(HDL_DIR)/core/mod_sim_exp_core.vhd \
                 $(HDL_DIR)core/mod_sim_exp_core.vhd \
                 $(HDL_DIR)/core/operand_dp.vhd \
                 $(HDL_DIR)core/operand_dp.vhd \
                 $(HDL_DIR)/core/operand_mem.vhd \
                 $(HDL_DIR)core/operand_mem.vhd \
                 $(HDL_DIR)/core/operand_ram.vhd \
                 $(HDL_DIR)core/operand_ram.vhd \
                 $(HDL_DIR)/core/operands_sp.vhd \
                 $(HDL_DIR)core/operands_sp.vhd \
                 $(HDL_DIR)/core/register_1b.vhd \
                 $(HDL_DIR)core/register_1b.vhd \
                 $(HDL_DIR)/core/register_n.vhd \
                 $(HDL_DIR)core/register_n.vhd \
                 $(HDL_DIR)/core/standard_cell_block.vhd \
                 $(HDL_DIR)core/standard_cell_block.vhd \
                 $(HDL_DIR)/core/stepping_logic.vhd \
                 $(HDL_DIR)core/stepping_logic.vhd \
                 $(HDL_DIR)/core/x_shift_reg.vhd \
                 $(HDL_DIR)core/x_shift_reg.vhd \
                 $(HDL_DIR)/core/sys_stage.vhd \
                 $(HDL_DIR)core/sys_stage.vhd \
                 $(HDL_DIR)/core/sys_last_cell_logic.vhd \
                 $(HDL_DIR)core/sys_last_cell_logic.vhd \
                 $(HDL_DIR)/core/sys_first_cell_logic.vhd \
                 $(HDL_DIR)core/sys_first_cell_logic.vhd \
                 $(HDL_DIR)/core/sys_pipeline.vhd \
                 $(HDL_DIR)core/sys_pipeline.vhd \
                 $(HDL_DIR)/core/mont_multiplier.vhd \
                 $(HDL_DIR)core/mont_multiplier.vhd \
 
 
 
 
##
##
# Testbench HDL file
# Testbench HDL files
##
##
TB_SRC_DIR = ../bench/vhdl/
TB_SRC_DIR = ../bench/vhdl/
TB_SRC =  $(TB_SRC_DIR)mod_sim_exp_core_tb.vhd
TB_SRC =        $(TB_SRC_DIR)mod_sim_exp_core_tb.vhd \
 
                        $(TB_SRC_DIR)msec_axi_tb.vhd
 
 
 
##
 
# Interface HDL files
 
##
 
IF_SRC_DIR = ../rtl/vhdl/interface/
 
IF_SRC =        $(IF_SRC_DIR)axi/msec_ipcore_axilite.vhd
 
 
#######################################
#######################################
all: mod_sim_exp
all: mod_sim_exp
 
 
clean:
clean:
Line 62... Line 69...
        vlib mod_sim_exp
        vlib mod_sim_exp
 
 
work_lib:
work_lib:
        vlib work
        vlib work
 
 
libs: mod_sim_exp work_lib
libs: mod_sim_exp_lib work_lib
 
 
mod_sim_exp_com: mod_sim_exp_lib
mod_sim_exp_com: mod_sim_exp_lib
        #echo --
        #echo --
        #echo building Modular Exponentiation Core
        #echo building Modular Exponentiation Core
        #echo --
        #echo --
        vcom $(VCOMOPS) -work mod_sim_exp $(CORE_SRC)
        vcom $(VCOMOPS) -work mod_sim_exp $(CORE_SRC)
        #echo Done!
        #echo Done!
 
 
mod_sim_exp_tb: work_lib
mod_sim_exp_tb: work_lib
        #echo --
        #echo --
        #echo building Modular Exponentiation Core Testbench
        #echo building Modular Exponentiation Core Testbenches
        #echo --
        #echo --
        vcom $(VCOMOPS) -work work $(TB_SRC)
        vcom $(VCOMOPS) -work work $(TB_SRC)
 
 
 
msec_if: work_lib
 
        #echo --
 
        #echo building Modular Exponentiation Core Interface
 
        #echo --
 
        vcom $(VCOMOPS) -work work $(IF_SRC)
 
 
mod_sim_exp: mod_sim_exp_com mod_sim_exp_tb
mod_sim_exp: mod_sim_exp_com mod_sim_exp_tb
        vsim -c -do mod_sim_exp.do -lib work mod_sim_exp_core_tb
        vsim -c -do mod_sim_exp.do -lib work mod_sim_exp_core_tb
 
 
 
mod_sim_exp_axi: mod_sim_exp_com msec_if mod_sim_exp_tb
 
        vsim -c -do mod_sim_exp.do -lib work msec_axi_tb
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