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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [sim/] [Makefile] - Diff between revs 90 and 94

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Rev 90 Rev 94
Line 1... Line 1...
#VCOM    = /usr/local/bin/vcom
#VCOM    = /usr/local/bin/vcom
VCOMOPS = -explicit -check_synthesis -2002 -quiet
VCOMOPS = -explicit -check_synthesis -2002 -quiet
 
VLOGOPS = -vopt -nocovercells
#MAKEFLAGS = --silent
#MAKEFLAGS = --silent
HDL_DIR = ../rtl/vhdl/
HDL_DIR = ../rtl/vhdl/
 
VER_DIR = ../rtl/verilog/
 
 
##
##
# hdl files
# hdl files
##
##
CORE_SRC =$(HDL_DIR)core/std_functions.vhd \
CORE_SRC =$(HDL_DIR)core/std_functions.vhd \
Line 42... Line 44...
                 $(HDL_DIR)core/sys_stage.vhd \
                 $(HDL_DIR)core/sys_stage.vhd \
                 $(HDL_DIR)core/sys_last_cell_logic.vhd \
                 $(HDL_DIR)core/sys_last_cell_logic.vhd \
                 $(HDL_DIR)core/sys_first_cell_logic.vhd \
                 $(HDL_DIR)core/sys_first_cell_logic.vhd \
                 $(HDL_DIR)core/sys_pipeline.vhd \
                 $(HDL_DIR)core/sys_pipeline.vhd \
                 $(HDL_DIR)core/mont_multiplier.vhd \
                 $(HDL_DIR)core/mont_multiplier.vhd \
 
                 $(HDL_DIR)core/pulse_cdc.vhd \
 
                 $(HDL_DIR)core/clk_sync.vhd \
 
 
 
VER_SRC =$(VER_DIR)generic_fifo_dc.v \
 
                 $(VER_DIR)generic_fifo_dc_gray.v
 
 
##
##
# Testbench HDL files
# Testbench HDL files
##
##
TB_SRC_DIR = ../bench/vhdl/
TB_SRC_DIR = ../bench/vhdl/
TB_SRC =        $(TB_SRC_DIR)mod_sim_exp_core_tb.vhd \
TB_SRC =        $(TB_SRC_DIR)mod_sim_exp_core_tb.vhd \
                        $(TB_SRC_DIR)msec_axi_tb.vhd
                        $(TB_SRC_DIR)msec_axi_tb.vhd \
 
                        $(TB_SRC_DIR)axi_tb.vhd
 
 
##
##
# Interface HDL files
# Interface HDL files
##
##
IF_SRC_DIR = ../rtl/vhdl/interface/
IF_SRC_DIR = ../rtl/vhdl/interface/
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mod_sim_exp_com: mod_sim_exp_lib
mod_sim_exp_com: mod_sim_exp_lib
        #echo --
        #echo --
        #echo building Modular Exponentiation Core
        #echo building Modular Exponentiation Core
        #echo --
        #echo --
 
        vlog $(VLOGOPS) -work mod_sim_exp $(VER_SRC)
        vcom $(VCOMOPS) -work mod_sim_exp $(CORE_SRC)
        vcom $(VCOMOPS) -work mod_sim_exp $(CORE_SRC)
        #echo Done!
        #echo Done!
 
 
mod_sim_exp_tb: work_lib
mod_sim_exp_tb: work_lib
        #echo --
        #echo --

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